Synthesis Log
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Function IID_IDispatch
IID_IDispatch = "{00020400-0000-0000-C000-000000000046}"
End Function
Function CLSID_Executor
CLSID_Executor = "Aldec.ExePlugIn.Generic.7"
End Function
Sub OpenPlugIn (progid, template, document, element, string)
Dim executor, command
Set executor = window.external.aldec.connector.OpenPlugIn(CLSID_Executor, IID_IDispatch)
command = "?Activate[][][][][]"
executor.ExecuteCommand command, ""
End Sub
Synthesis Log
Created on 13:03:21 04/03/15
Running XST Synthesis...
Please wait...
Release 6.3i - xst G.35
Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to .
CPU : 0.00 / 0.44 s | Elapsed : 0.00 / 0.00 s
--> Parameter xsthdpdir set to e:/projekty_vhdl/proj/projmm/synthesis/xst
CPU : 0.00 / 0.44 s | Elapsed : 0.00 / 0.00 s
-->
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) HDL Analysis
4) HDL Synthesis
5) Advanced HDL Synthesis
5.1) HDL Synthesis Report
6) Low Level Synthesis
7) Final Report
7.1) Device utilization summary
7.2) TIMING REPORT
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : p1.prj
Input Format : mixed
Ignore Synthesis Constraint File : no
---- Target Parameters
Output File Name : p1
Output Format : NGC
Target Device : xcv50bg256-6
---- Source Options
Top Module Name : p1
Automatic FSM Extraction : yes
FSM Encoding Algorithm : Auto
Resource Sharing : yes
FSM Style : lut
RAM Extraction : yes
RAM Style : auto
ROM Extraction : yes
ROM Style : auto
Mux Extraction : yes
Mux Style : auto
Decoder Extraction : yes
Priority Encoder Extraction : yes
Shift Register Extraction : yes
Logical Shifter Extraction : yes
XOR Collapsing : yes
Multiplier Style : lut
Automatic Register Balancing : no
---- Target Options
Add IO Buffers : yes
Global Maximum Fanout : 100
Add Generic Clock Buffer(BUFG) : 4
Register Duplication : yes
Equivalent register Removal : yes
Pack IO Registers into IOBs : auto
Slice Packing : yes
---- General Options
Optimization Goal : speed
Optimization Effort : 1
Global Optimization : allclocknets
RTL Output : yes
Write Timing Constraints : no
Keep Hierarchy : no
Hierarchy Separator : _
Bus Delimiter : <>
Case Specifier : maintain
Slice Utilization Ratio : 100
Slice Utilization Ratio Delta : 5
---- Other Options
verilog2001 : yes
cross_clock_analysis : no
Read Cores : yes
tristate2logic : yes
Optimize Instantiated Primitives : no
=========================================================================
=========================================================================
* HDL Compilation *
=========================================================================
Compiling vhdl file e:/projekty_vhdl/proj/projmm/synthesis/./../src/p1.vhd in Library work.
Entity <p1> (Architecture <p1>) compiled.
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing Entity <p1> (Architecture <p1>).
Entity <p1> analyzed. Unit <p1> generated.
=========================================================================
* HDL Synthesis *
=========================================================================
Synthesizing Unit <p1>.
Related source file is e:/projekty_vhdl/proj/projmm/synthesis/./../src/p1.vhd.
WARNING:Xst:647 - Input <CLK> is never used.
WARNING:Xst:643 - The result of a 6x5-bit multiplication found at line 45 is partially used. Only the 10 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
Found 6-bit adder for signal <C>.
Found 6-bit subtractor for signal <D>.
Found 6x5-bit multiplier for signal <$n0000> created at line 45.
Summary:
inferred 2 Adder/Subtracter(s).
inferred 1 Multiplier(s).
Unit <p1> synthesized.
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
Advanced RAM inference ...
Advanced multiplier inference ...
INFO:Xst:1784 - HDL ADVISOR - Multiplier(s) is(are) identified in your design. You can improve the performance of your multiplier by using the pipeline feature available with mult_style attribute.
Advanced Registered AddSub inference ...
Dynamic shift register inference ...
=========================================================================
HDL Synthesis Report
Macro Statistics
# Multipliers : 1
6x5-bit multiplier : 1
# Adders/Subtractors : 2
6-bit subtractor : 1
6-bit adder : 1
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
Optimizing unit <p1> ...
Loading device for application Xst from file 'v50.nph' in environment D:/Xilinx.
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block p1, actual ratio is 2.
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : p1.ngr
Top Level Output File Name : p1
Output Format : NGC
Optimization Goal : speed
Keep Hierarchy : no
Design Statistics
# IOs : 34
Macro Statistics :
# Adders/Subtractors : 2
# 6-bit adder : 1
# 6-bit subtractor : 1
# Multipliers : 1
# 6x5-bit multiplier : 1
Cell Usage :
# BELS : 124
# GND : 1
# LUT1 : 3
# LUT2 : 18
# LUT3 : 7
# LUT4 : 11
# MULT_AND : 12
# MUXCY : 36
# VCC : 1
# XORCY : 35
# IO Buffers : 33
# IBUF : 11
# OBUF : 22
=========================================================================
Device utilization summary:
---------------------------
Selected Device : v50bg256-6
Number of Slices: 21 out of 768 2%
Number of 4 input LUTs: 39 out of 1536 2%
Number of bonded IOBs: 33 out of 184 17%
=========================================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
No clock signals found in this design
Timing Summary:
---------------
Speed Grade: -6
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 15.847ns
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
-------------------------------------------------------------------------
Timing constraint: Default path analysis
Delay: 15.847ns (Levels of Logic = 15)
Source: A<2> (PAD)
Destination: E<9> (PAD)
Data Path: A<2> to E<9>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 9 0.768 1.908 A_2_IBUF (A_2_IBUF)
LUT2:I0->O 1 0.573 0.000 Mmult__n0000_inst_lut2_21 (Mmult__n0000_inst_lut2_2)
MUXCY:S->O 1 0.653 0.000 Mmult__n0000_inst_cy_7 (Mmult__n0000_inst_cy_7)
MUXCY:CI->O 1 0.044 0.000 Mmult__n0000_inst_cy_8 (Mmult__n0000_inst_cy_8)
XORCY:CI->O 2 0.418 1.206 Mmult__n0000_inst_sum_9 (Mmult__n0000_N116)
LUT3:I0->O 1 0.573 0.000 Mmult__n0000_inst_lut3_01 (Mmult__n0000_inst_lut3_0)
MUXCY:S->O 1 0.653 0.000 Mmult__n0000_inst_cy_14 (Mmult__n0000_inst_cy_14)
MUXCY:CI->O 1 0.044 0.000 Mmult__n0000_inst_cy_15 (Mmult__n0000_inst_cy_15)
MUXCY:CI->O 1 0.044 0.000 Mmult__n0000_inst_cy_16 (Mmult__n0000_inst_cy_16)
MUXCY:CI->O 1 0.044 0.000 Mmult__n0000_inst_cy_17 (Mmult__n0000_inst_cy_17)
XORCY:CI->O 1 0.418 1.035 Mmult__n0000_inst_sum_18 (Mmult__n0000_inst_lut2_10)
LUT1:I0->O 1 0.573 0.000 Mmult__n0000_inst_lut2_10_rt (Mmult__n0000_inst_lut2_10_rt)
MUXCY:S->O 0 0.653 0.000 Mmult__n0000_inst_cy_26 (Mmult__n0000_inst_cy_26)
XORCY:CI->O 1 0.418 1.035 Mmult__n0000_inst_sum_27 (E_9_OBUF)
OBUF:I->O 4.787 E_9_OBUF (E<9>)
----------------------------------------
Total 15.847ns (10.663ns logic, 5.184ns route)
(67.3% logic, 32.7% route)
=========================================================================
CPU : 1.53 / 2.39 s | Elapsed : 1.00 / 2.00 s
-->
Total memory usage is 56440 kilobytes
Processing design ...
Writing file p1.vhd completed.
Synthesis finished with warnings.
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