design
The best of
ideas design ideas
8Check it out at:
www.edn.com
Edited by Bill Travis
Circuit provides 4- to 20-mA loop
for microcontrollers
Robert Most, Dow Corning Corp, Auburn, MI
15V 15V
he 4- to 20-mA current loop is ubiq-
15V
uitous in the world of controls in
100
1%
Tmanufacturing plants. Discrete log-
ic, microprocessors, and micro-
6
Figure 1 _
controllers easily cover the digital
680
100
1/2 7
Q3
1M 1%
TL032
portions of control schemes, such as lim-
2N3906
5
8.2k 8 +
27k
3
it switches, pushbuttons, and signal
FROM + 4
1/2
1
PROCESSOR
lights. Interfacing a 4- to 20-mA output IOUT
100k
TL032 Q2
TIMER
2 Q1
4.7 F
_
to a rudimentary microcontroller can be
2N3906
2N3904
56k
problematic. A built-in A/D converter
RL
TO
would be nice, but such a device is some-
PROCESSOR
140
27k
times unavailable in the  economy line INPUT PORT
1%
of these processors. Serial 4- to 20-mA
chips exist but are relatively expensive
and require serial programming and in- This configuration provides both a 4- to 20-mA loop and an open-circuit indication.
volve microcontroller overhead. Most
lower end chips lack dedicated serial ditional voltage swing below ground po- back through its emitter-base junction
ports and require pin-programming. tential to keep it in its active region and and through the 680 resistor to the op
This circuit is a low-cost alternative does not cut off. The emitter resistor of amp. The voltage developed across the
that provides not only a 4- to 20-mA out- npn transistor Q1 sets the current span of 680 resistor turns on Q2, resulting in
put, but also a digital feedback signal that the circuit. With a 5V drive from the mi- a logic-one feedback to the microcon-
indicates an open wire in the current loop crocontroller, the output current is 20 troller. Note that the open loop requires
(Figure 1). One output-port pin sets the mA. A grounded input results in less than at least 1 mA of current for the open in-
current, and one input-port pin monitors 1 mA. A duty cycle of 12.5% drives the dication to function, which is below the
an open circuit in the loop wire. The cir- loop at 4 mA and exhibits linear control normal 4 mA a  zero output condi-
cuit does not require the open-loop feed- to full scale. Although it may not be
back portion of the circuit for the current mandatory, most current loops prefer a
Circuit provides 4- to 20-mA loop
loop to operate; you can omit it for fur- grounded return path. The purpose of
for microcontrollers........................................89
ther cost savings. the second operational amplifier is to
The circuit derives its drive from a sim- provide a current source, rather than the Minimize the short-circuit current pulse
ple timer output in the microcontroller. current sink of the first stage, and the in a hot-swap controller ..............................90
The duty cycle of the timer determines grounded return path. Hence, pnp tran-
Reduce EMI by sweeping
the output current of the circuit. The in- sistor Q3 provides this high-side drive.
a power supply s frequency ........................92
put RC network in front of the first op- Bipolar-junction transistors Q1 and Q3
Get just enough boost voltage ..................94
erational-amplifier signal conditions the meet cost considerations, but you could
pulse train from the processor, so that the also use MOSFETs for slightly better per- Processor s PWM output controls
op amp interprets it as a dc voltage. In ad- formance.
LCD/LED driver ..............................................96
dition, the network ensures that the min- The open-loop feedback portion of
Method provides automatic
imum input voltage is close to 100 mV, this circuit lets the microcontroller
machine shutdown........................................98
even if the input is at ground potential. know that a fault condition exists on the
Circuit makes simple high-voltage
This minimum voltage ensures that the line. The processor can then execute
inverter ..........................................................100
feedback loop of the first op amp does alarm, shutdown, or other control func-
not fold back to the positive rail when tions to mitigate possible safety con- Publish your Design Idea in EDN. See the
What s Up section at www.edn.com.
you cut off npn transistor Q1. If you use cerns. When an open-loop condition oc-
a dual supply, the transistor has the ad- curs, Q3 shunts the entire loop current
www.edn.com May 27, 2004 edn 89
|
design
ideas
tion for this type of control system. microcontroller you select has a built- tion is important if you use a single-
Response time for a step change is ap- in A/D converter, response time can de- supply topology. An operational ampli-
proximately 500 msec, which is accept- crease by a couple of orders of magni- fier that can maintain stability close to
able for most current-loop control de- tude with the elimination of the in- its negative, or ground, rail is an im-
vices, such as control valves. If the put-filtering network. Op-amp selec- portant asset.
Minimize the short-circuit current pulse
in a hot-swap controller
Jim Sherwin and Thong Huynh, Maxim Integrated Products, Sunnyvale, CA
ecause of internal circuit- tor chip. The circuit of Figure 5
M1
RS
FDS7788
breaker delay and limited can limit short-circuit current to
0.006
BMOS-gate pulldown current, approximately 100A for less than
12VIN 12VOUT
many hot-swap controllers do not 200 nsec. The pnp transistor, Q1A,
limit current during the first 10 to which triggers when the voltage
50 sec following a shorted out- across RS reaches approximately
put. The result can be a brief flow IN SENSE GATE 600 mV, drives the npn transistor,
of several hundred amperes. A Q1B,to quickly discharge M1 s gate
STAT
ON POR
MAX4272ESA
simple external circuit can count- capacitance. The steep voltage
CSPD GND CTIM
er this problem by minimizing the waveform aids quick triggering of
initial current spike and terminat- C1 the pnp transistor.
22 nF
ing the short circuit The oscilloscope s ground lead
NC
Figure 1
within 200 to 500 nsec. A introduces an artifact, which ap-
typical 12V, 6A, hot-swap-con- A typical hot-swap controller circuit exhibits a 30- sec short- pears as the leading-edge oscilla-

troller circuit contains, as do many circuit current pulse of 400A peak. tion in Figure 6. Again, as in Fig-
others, slow and fast comparators ure 4, the apparent reverse-
with trip thresholds of 50 and 200 mV resistances. The waveform recorded dur- overshoot current and the steep rise in the
(Figure 1). The 6-m sense resistor, RS, ing a short circuit indicates a peak cur- waveform of Figure 6 arise from parasitic
allows a nominal slow-comparator trip at rent of 400 from the 2.4V peak across RS, series inductance in the sense-resistor
8.3A for overload conditions and a fast- decreasing to 100A in 28 sec (Figure 2). chip. C2 connects between the gate and
comparator trip at 33.3A for short cir- You can limit the short-circuit current source of M1 to reduce the positive-tran-
cuits. Only circuit resistances limit the duration to less than 0.5 sec by adding sient step voltage applied to the gate dur-
initial short-circuit current spike during a Darlington pnp transistor, Q1, to speed ing a short circuit. Zener diode D1 reduces
a period that includes the fast-compara- the gate discharge (Figure 3). D1 allows ID(ON) by limiting VGS to less than the 7V
tor delay and the 30 sec it takes to com- the gate to charge normally at turn-on, available from the MAX4272.Although D1
plete interruption of the short circuit by but, at turn-off, the con-
M1
discharging M1 s gate capacitance. Vari- troller s 3-mA gate-dis-
RS
FDS7788
0.006
ous elements, such as RS and the on-re- charge current is direct-
12VIN 12VOUT
sistance of M1, contribute to the circuit ed to the base of Q1. Q1
MMBTA64FSTR-ND
then acts quickly to dis-
Q1
FLAG-COMPARATOR charge the gate, in less
TRIGGER POINT
than 100 nsec. Thus, the D1
MMBD4148
high-current portion of
the short circuit is limit-
ed to slightly more than
IN SENSE GATE
the fast comparator s de-
ON MAX4272ESA STAT POR
lay time of 350 nsec. The
VOLTAGE MEASURED ACROSS RS=6 m .
apparent reverse over-
CSPD GND CTIM
shoot current and the
C1
steep rise in the wave-
1V M5 SEC CH1  200 mV
NC 22 nF
form of Figure
Figure 2 Figure 3
The short-circuit current 4 arise from
in Figure 1 is 400A, decreasing to 100A in parasitic series induc- The addition of Q1 increases the gate-pulldown current, lim-


28 sec. tance in the sense-resis- iting the short-circuit-current duration to less than 0.5 sec.
90 edn May 27, 2004 www.edn.com
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design
ideas
M1
RS FDS7788
STEEP RISE AND
0.006
REVERSE OVERSHOOT
IN SENSE-RESISTOR
12VIN 12VOUT
VOLTAGE MEASUREMENT
C2
IS AN ARTIFACT OF
SENSE-RESISTOR PARA-
R1 R3
D1 100 nF
SITIC INDUCTANCE.
100 5.1V 1k
Q1B
R2
100
FFB2227A
Q1A
M 250 nSEC CH1  360 mV
IN SENSE GATE
Figure 5
ON MAX4272ESA STAT POR
Figure 4
This hot-swap
The steep rise and reverse
CSPD GND CTIM
controller has
overshoot in Figure 3 s circuit are artifacts of
fast limiting of
sense-resistor parasitic inductance. C1
NC 22 nF
short-circuit-
current peaks.
is rated at 5.1V when biased at 5 mA, it
limits VGS to approximately 3.4V in this
circuit because only 100 A of gate-charg- slightly more complex circuit (Figure 5)
ing current (zener-bias current) is avail- reduces the peak short-circuit current to
able from the IC. The limited VGS lowers 100A, as well as truncating the pulse width
ID(ON) at some expense to on-resist- to less than 200 nsec. You can apply either
ance and allows a quicker turn-off of technique to most hot-swap-controller
M1. You could also use D1 and C2 to some circuits. Individual results vary according
advantage in figures 1 and 3, to reduce to the impedance of the power source, the
ID(ON) during short circuits. impedance of the short circuit, and the
Either of the two circuits can protect a quality and attack time of the short circuit
M 100 nSEC CH1  520 mV
backplane power source by minimizing itself. Note that it is inordinately difficult
the energy dissipated when a hot-swap- to achieve a repeatable low-resistance short
controller circuit incurs a short circuit.The circuit by manual manipulation of a
Figure 6
This waveform depicts the
simpler circuit (Figure 3) dramatically shorting bar. You require careful lay-
short-circuit-current peaks for the circuit in
shortens the short-circuit-current interval out and low-ESR capacitors to create a
Figure 4.
to somewhat less than 500 nsec, and the power source with very low ESR.
Reduce EMI by sweeping a power supply s frequency
John Betten, Texas Instruments, Dallas, TX
witching power supplies can be but at diminished amplitudes. The sim- parator output trips to a low state. The
notorious noise generators. You ple circuit in Figure 1 makes the switch- voltage on R6 instantly drops to a lower
Sshould prevent this noise, which is ing converter operate over multiple fre- reference level because R5 is now in par-
conducted, radiated, or both, from re- quencies rather than one, thereby allel with R6. C3 begins to discharge to-
turning to the input source, where it can reducing the time average at any one fre- ward this new reference level because R3
potentially wreak havoc on other devices quency. This scheme effectively lowers is simultaneously in parallel with C3. The
operating from the same input power. the peak emissions. cycle repeats after C3 discharges to the
The goal of an EMI (electromagnetic-in- The circuit in Figure 1 is a self-starting voltage on R6 when the comparator out-
terference) filter is to block this noise and oscillator with an oscillation frequency of put reopens.You must carefully select the
provide a low-impedance path back to approximately 500 Hz. When you apply components to ensure that the two volt-
the noise source. The larger the noise, the power, C3 begins to charge up from 0V, age-reference states of R6 are lower than
greater the size, expense, and difficulty of and the output of the TL331 comparator the upper and lower possible charge
the filter design. Power supplies that op- is in a high-impedance state because its states of C3. The circuit uses C3 to adjust
erate at a fixed frequency have their noninverting input sees a higher voltage the oscillator frequency; you should se-
largest EMI emission at this fundamen- than that of the inverting input. As C3 lect C3 to have a lower value than C2. The
tal, fixed frequency. Emissions also occur charges, its voltage crosses the voltage ref- oscillator s frequency is approximately
at multiples of the switching frequency erence of the R1-R6 divider, and the com- equal to
92 edn May 27, 2004 www.edn.com
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design
ideas
5V BIAS
C1 R1 R2
0.1 F 49.9k
10k
R3
10k
IC1
UCC3813
5 1
RT 1
8
4
COMP REF
IC1 3 13.7k
C2
2 7
TL331DBV R4
FB VCC
1 F
24.9k
Capacitor C2 ac-couples the ramp 3 6
R5 2
CS OUT
4 5
6.04k
voltage of C3 into the UCC3813 s oscil-
RC GND
lator pin. The injected signal adds to the
CT
R6 C3
330 pF
4.99k 0.1 F
charging current of CT during its posi-
tive portion (ac signal), thus increasing
the controller s operating frequency.
During the injected signal s
Figure 1
negative portion, some of CT s
A low-frequency oscillator ramp, injected into the RC pin, modulates the supply s switch-
charging current disappears, slowing
ing frequency.
the controller s operating frequency.
Figure 2 shows the effects of the inject- the frequency-sweep rate. the circuit below the power converter s
ed signal on the charging of CT. R4 con- The differential EMI-current measure- low-frequency limits, or saturation of
trols the magnitude of the current that ment of Figure 3 (1 dB V 1 dB A) magnetics may occur. This circuit demon-
is injected. Reducing R4 s value increas- shows the before-and-after effects of strates a low-cost, small-area approach to
es the range, or spread, of the operat- adding the frequency-shifting oscillator. reducing conducted-EMI emissions.
ing frequency around its nominal fixed This design easily achieves a 10-
frequency. The injected signal s oscilla- dB A reduction with a 12-kHz
tion frequency, which C3 sets, controls sweep window. A wider win-
dow further reduces EMI, but
1
1 SEC
the modulator frequency may
0.50V
be noticeable in the converter s
10115 SWPS
output ripple voltage. It is also
desirable to make the injected
ramp voltage as linear in shape
as possible to prevent the
switching converter from
1 SEC BWL
spending excess time at its
1 50 mV DC
2 50 mV DC
switching-frequency limits. The
200 mSAMPLES/SEC
3 0.1V DC
Ą% STOPPED
4 0.5V DC 1 DC 1.39V nonlinearity can result in an
EMI response with two
Figure 2 Figure 3
The external oscillator varies distinct frequencies. You The EMI of the flyback converter
the charging of the timing capacitor. must take care not to operate differs with and without external modulation.
Get just enough boost voltage
Kieran O Malley, On Semiconductor, East Greenwich, RI
VIN 14V
dding a current-mirror circuit to
a typical boost circuit allows you to
+
L1
Aselect the amount of boost voltage
C1
VOUT 24V
22 H
22 F
and to ensure a constant difference be- SHUTDOWN
5
D1
VOC
tween the input and the output voltages 4
8
VSW
SS
BC856BDWLT1
(Figure 1). This circuit is useful for high-
+
3 IC1 MBRS120T3
C3
NC
side-drive applications, in which a sim-
CS5171
22 F
ple voltage doubler is unacceptable be-
2
1 Q1A Q1B
VFB
VC
cause of the voltage range of the
C2 AGND PGND R4
R2
components involved or where the input
8.2k
0.01 F 10k
6 7
voltage can vary widely. You can also use
R1
the circuit at the front end of a 4.7k R3
Figure 1
1.27k
power supply to ensure that the
PWM controller has enough voltage to
start correctly in low-input-voltage con- Adding a current-mirror circuit to a boost circuit allows you to get just enough boost voltage.
94 edn May 27, 2004 www.edn.com
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design
ideas
ditions. The circuit maintains a 10V dif- of 65V. In this case, VIN 14V (nominal), you use a 10-k resistor.
ference between VIN and VOUT, but you so you need VOUT to be 24V (nominal). Q1B mirrors the current and sets up the
can easily change it to provide other volt- First, calculate a value for R2, thus estab- feedback voltage to the PWM circuit. The
ages. The PWM circuit in Figure 1 is the lishing the reference current. If you select CS5171 has an internal voltage of 1.28V
CS5171 from On Semiconductor (www. a reference current of 1 mA, you obtain (typical), so R3 yields the correct feedback
onsemi.com), but you can use the idea voltage when the current flowing
with any boost circuit. The current-mir- through it is 1 mA. In this case, by select-
ror circuit, comprising the dual-pnp ing 1.27 k for R3, you obtain an output
transistor, Q1, and the associated resis- voltage of 24V. As VIN varies, VOUT tracks
tors, establishes a current that depends on it and maintains a 10V difference be-
the voltage difference between VIN and tween the input and the output. R4 helps
VOUT. The dual-pnp transistor has a VCEO Because the output voltage is not critical, reduce the power dissipation in Q1B.
Processor s PWM output controls LCD/LED driver
Joe Neubauer, Maxim Integrated Products, Sunnyvale, CA
he PWM (pulse-width-modulation) LED driver (Figure 3). The circuit com- voltage, VCONT:
output available from many micro- prises simply the PWM source, capacitor
Tprocessors is based on an internal 8- C, and resistors RD and RW. For CMOS
or 16-bit counter and features a pro- circuits, you calculate the open-circuit
grammable duty cycle. It is suitable for output voltage as VCONT D VDD, where
adjusting the output of an LCD driver VCONT is the control circuit s output volt- where VREF is the reference voltage at the
(Figure 1), a negative-voltage LCD driv- age, D is the PWM duty cycle, and VDD is feedback input.
er (Figure 2), or a current-controlled the logic-supply voltage. The control cir- Bear in mind that the initial charge on
cuit s output im- filter capacitor C produces a turn-on
VIN
pedance is the sum transient. The capacitor forms a time
IN 3.3V
MAIN
+
300 mA
of the resistor values constant with RCONT, which causes the
C1 SWIN C3
RD and RW: RCONT output to initialize at a voltage higher
3.3V RD RW. For the cir- than that intended. You can minimize
SDIG
200 mA
REF
cuit of Figure 1, the this overshoot by scaling the value of RD
C5
output voltage, as high as possible with respect to R1 and
C8 MAX1552
1.5V
COR1 VOUT, is a function R2. As an alternative, the microprocessor
200 mA
C4
of the PWM average can disable the LCD until the PWM volt-
ON
SDIG ENSD
1.8V
VIN
COR2
OFF
20 mA
5V
C6
ON
ENC2
COR2
+
OFF
SW
RSENSE
ON C9
LCD ENLCD
LCD
L1 0.1 F 1
OFF 8
20V V
CS
D1
1 mA
2
MAIN
LX 7
ADJ DHI
C2
R3 R4
C7 R1 DIGITAL
VOUT
MAX749
ADJUST
RESET 3
RS LFB
6
CTRL DLOW
OUTPUT
R2
ON/OFF
GND
LOW-BATTERY LBO +
4
5
OUTPUT FB
GND
Figure 2
RFB
CONNECTION FOR
PWM-CONTROLLED
LCD BIAS
CCOMP
CONNECTION FOR
RD
VDD PWM-CONTROLLED
RW
LCD BIAS
FROM
PROCESSOR
RD
VDD
PWM OUTPUT
RW
0 C
FROM
PROCESSOR
PWM OUTPUT
C
0
Figure 1
This configuration provides negative-output-voltage LCD drive.
This simple circuit provides positive-output voltage LCD drive.
96 edn May 27, 2004 www.edn.com
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design
1 F 1 F
ideas
C1F C1N C2P C2N
VIN
2.7 TO 5.5V
1 /1.5 OUT
REGULATING CHARGE PUMP
+ 4.7 F
age stabilizes. For Figure 2, the output
1 F
voltage, VOUT, is a function of the PWM
MAXIM
average voltage, VCONT:
MAX1570
LED1
EN1
ON/OFF
LED2
AND REFERENCE
EN2 LOW-DROPOUT
DIMMING AND
LED3
CURRENT
CONTROL
where VREF is the reference voltage at
REGULATORS
Figure 3
SET LED4
the feedback input. For Figure 3, the
LED5
RSET
output current is a function of the PWM
average voltage, VCONT:
GND PGND
CONNECTION FOR
PWM-CONTROLLED
LCD BIAS
VDD RW RD
FROM
PROCESSOR
PWM OUTPUT
C
where VREF is the reference voltage at the 0
Set output and K is the current-scaling
PWM combines with current control in this LED-driver circuit.
factor.
RD isolates the capacitor from the feed- point, the following equation defines the mize ripple voltage at the output, you
back loop in the PWM-control methods. lowpass filter s cutoff frequency: fC should set the cutoff frequency at least two
Assuming a stable voltage at the feedback 1/(2 RC), where R RD||RW. To mini- decades below the PWM frequency.
Method provides automatic machine shutdown
Jean-Bernard Guiot, Mulhouse, France
ome machines need to run for long 15 of relay K2T incurs a delay before open- tacts of K2T open, K1 turns off, and the ma-
periods and therefore may finish ing, because K2T is a time-delay relay, the chine completely turns off. The varistors,
Stheir work in the middle of the night machine stays on during the delay time. VR1,suppresses voltage spikes.You must se-
or during the weekend. For the time re- This delay allows a second contact of KSTOP lect VR1,K1,K2T, and H1 in accordance with
maining, until the operator returns, the to control an automatic telephone dialer the power-mains voltage and the power
machines stay idle, uselessly consuming (not shown) to inform the remotely locat- rating of the machine.You select KSTOP ac-
power. This Design Idea allows a machine ed operator and allows the process to fin- cording to the controller s output (the re-
to completely shut itself down after fin- ish supplementary tasks, such as cooling lay coil) and the power-mains voltage (the
ishing its work. In addition, the method down, removing chips, allowing coolant to relay contacts). The circuit has worked sat-
allows for informing the machine opera- flow back into the tanks, for example. isfactorily in hundreds of machines over
tor by phone. You insert the circuit into Once the delay time expires, the con- a five-year period.
the area that Figure 1 indicates as a
ADD CIRCUIT IN DASHED LINES TO EXISTING MACHINE
dashed line into the main supply line of
the machine. The relay, KSTOP, connects to
FROM
1 2
TO
POWER
a free output of the programmable con-
MACHINE
3 4
MAINS
troller of the machine.You must program
5 6
K1
the controller in such a way that relay
FUSE 1A
KSTOP is energized as long as the process
is running. In normal operation, switch
VCC
A1
S1 stays in manual position; thus, the
MANUAL AUTO
1 18 14
K2T KSTOP
KSTOP
power contactor, K1, is on, and the ma-
chine receives power. When an operator S1 215 11
A2
starts the process, relay KSTOP energizes,
and the indicator, H1, lights, signaling the
operator that switch S1 is ready for
Figure 1
operation. The timer relay, K2T, is FROM
A1 A1 B1
1
CONTROLLER
also on, closing its contact 18-15. Switch-
K1 VR1 K2T H1
2
ing S1 to automatic now has no effect.
A2 A2
At the end of the process,relay KSTOP and
indicator H1 turn off. Because contact 18- This circuit allows a machine to completely shut itself off after doing its assigned task.
98 edn May 27, 2004 www.edn.com
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design
ideas
Circuit makes simple high-voltage inverter
Francesc Casanellas, Aiguafreda, Spain
L1
simple high-voltage MOSFET in-
30 H
verter solves the problem of driving R1 D1
TO THE OTHER INVERTER
340V
Aa high-side MOSFET, using a low-
4.7
BYV26C
+ D2
voltage transistor, Q1, and a special
C1 C2
12V
arrangement involving D6 (Figure 1). 680 F 220 nF
BYV26C R2 C3 +
This inverter is much faster than those
D3 22k 22 F
D4
that optocouplers drive, so dead-time
1N4148
BYV28-50
problems are minimal. The inverter has
Q1
D5
the usual blocking diodes D4 and D6, and
2N2907A
C4 UF5406
R3 R4
the parallel diodes D5 and D8. Q3 provides 100 pF
1M
22
the turn-off signal to Q2. When Q3 turns Q2
IRFP450
on, Q2 s gate short-circuits to ground
through R4. R4 limits current and damp-
D6 OUTPUT
ens oscillations. Q2 s gate dis-
BYV28-50
Figure 1
charges quickly; only the value
D7
of R4 limits discharge time. Q1 stays off, 1N4148
D8
thanks to R2, and C3 charges to 12V This circuit is probably the
Q3 UF5406
PWM
through D2. The gate pulse creates a cur- simplest high-voltage IRFP450
R5
rent through C4, and D3 protects the inverter you can build. 22
100 edn May 27, 2004 www.edn.com
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design
ideas
12V
base-emitter junction of Q1. inverter with 150% overload ca-
In the turn-on of Q2, the fol- pacity. If you change the MOS-
lowing scenario occurs: When FET, the value of C4 has to change
1k
the control input, PWM, according to the total gate charge
2N2222A
Figure 2
goes low, Q3 quickly turns plus the output capacitance of Q3,
off, thanks to D7. A displacement which is much lower and, in fact,
2.2 nF
current, C4 dV/dt, flows negligible. Q1 amplifies the ca-
300
OUTPUT
through C4 to the base of Q1. Q1 pacitor current, so C4 is propor-
1N4148
charges the output capacitance tional to QG2 hFE1. Make C4 s val-
INPUT
of Q3 and the gate capacitance of ue no higher than necessary,
2.2k
2N2222A
Q2, and Q2 turns on. C3 supplies because the base current in Q1
560
the collector current. If the pe- would be too high. To obtain all
riod is long, Q1 keeps conduct- the speed advantages of the cir-
ing and compensating the leak- cuit, the PWM signal should be
age of Q3. If D6 were a Schottky able to quickly drive Q3. If neces-
This buffer enhances speed at the PWM input of Figure
diode, which is leaky, you would sary, you can use a buffer circuit
1 s circuit.
have to reduce the value of R1. A (Figure 2). You can drive the cir-
short cross-conduction period exists be- current spikes. The inductor needs a cuit with a single CMOS gate. The circuit
tween the two MOSFETs, a phenomenon snubber comprising D1, R1, and C2. Note in Figure 1 is probably the simplest high-
that is more apparent when Q3 turns off that the inductor value is conservative voltage inverter you can design. It has
and Q2 turns on. A small inductor, L1, in and can be smaller. served in thousands of three-phase mo-
series with the main supply limits the The values are for a 370W, three-phase tor drives from 0.37 to 0.75 kW.
102 edn May 27, 2004 www.edn.com
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