Synthesis Log
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Function IID_IDispatch
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Function CLSID_Executor
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End Sub
Synthesis Log
Created on 13:05:23 12/13/15
Running XST Synthesis...
Please wait...
Release 6.3i - xst G.35
Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to .
CPU : 0.00 / 0.42 s | Elapsed : 0.00 / 0.00 s
--> Parameter xsthdpdir set to e:/projekty_vhdl/miroslawcz_proj/miroslawcz_proj/synthesis/xst
CPU : 0.00 / 0.42 s | Elapsed : 0.00 / 0.00 s
-->
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) HDL Analysis
4) HDL Synthesis
5) Advanced HDL Synthesis
5.1) HDL Synthesis Report
6) Low Level Synthesis
7) Final Report
7.1) Device utilization summary
7.2) TIMING REPORT
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : calyuklad.prj
Input Format : mixed
Ignore Synthesis Constraint File : no
---- Target Parameters
Output File Name : calyuklad
Output Format : NGC
Target Device : xcv50bg256-6
---- Source Options
Top Module Name : calyuklad
Automatic FSM Extraction : yes
FSM Encoding Algorithm : Auto
Resource Sharing : yes
FSM Style : lut
RAM Extraction : yes
RAM Style : auto
ROM Extraction : yes
ROM Style : auto
Mux Extraction : yes
Mux Style : auto
Decoder Extraction : yes
Priority Encoder Extraction : yes
Shift Register Extraction : yes
Logical Shifter Extraction : yes
XOR Collapsing : yes
Multiplier Style : lut
Automatic Register Balancing : no
---- Target Options
Add IO Buffers : yes
Global Maximum Fanout : 100
Add Generic Clock Buffer(BUFG) : 4
Register Duplication : yes
Equivalent register Removal : yes
Pack IO Registers into IOBs : auto
Slice Packing : yes
---- General Options
Optimization Goal : speed
Optimization Effort : 1
Global Optimization : allclocknets
RTL Output : yes
Write Timing Constraints : no
Keep Hierarchy : no
Hierarchy Separator : _
Bus Delimiter : <>
Case Specifier : maintain
Slice Utilization Ratio : 100
Slice Utilization Ratio Delta : 5
---- Other Options
verilog2001 : yes
cross_clock_analysis : no
Read Cores : yes
tristate2logic : yes
Optimize Instantiated Primitives : no
=========================================================================
=========================================================================
* HDL Compilation *
=========================================================================
Compiling vhdl file e:/projekty_vhdl/miroslawcz_proj2/synthesis/./../src/przetworzenie.vhd in Library work.
Architecture przetworzenie of Entity przetworzenie is up to date.
Compiling vhdl file e:/projekty_vhdl/miroslawcz_proj2/synthesis/./../src/ukladoperacyjny.vhd in Library work.
Architecture ukladoperacyjny of Entity ukladoperacyjny is up to date.
Compiling vhdl file e:/projekty_vhdl/miroslawcz_proj2/synthesis/./../compile/ukladsterujacy.vhd in Library work.
Architecture ukladsterujacy_arch of Entity ukladsterujacy is up to date.
Compiling vhdl file e:/projekty_vhdl/miroslawcz_proj2/synthesis/./../compile/calyuklad.vhd in Library work.
Architecture calyuklad of Entity calyuklad is up to date.
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing Entity <calyuklad> (Architecture <calyuklad>).
WARNING:Xst:753 - e:/projekty_vhdl/miroslawcz_proj2/synthesis/./../compile/calyuklad.vhd line 87: Unconnected output port 't' of component 'ukladoperacyjny'.
Entity <calyuklad> analyzed. Unit <calyuklad> generated.
Analyzing Entity <przetworzenie> (Architecture <przetworzenie>).
Entity <przetworzenie> analyzed. Unit <przetworzenie> generated.
Analyzing Entity <ukladoperacyjny> (Architecture <ukladoperacyjny>).
Entity <ukladoperacyjny> analyzed. Unit <ukladoperacyjny> generated.
Analyzing Entity <ukladsterujacy> (Architecture <ukladsterujacy_arch>).
Set property "fsm_extract = yes" for signal <Sreg0>.
Set property "fsm_fftype = d" for signal <Sreg0>.
Entity <ukladsterujacy> analyzed. Unit <ukladsterujacy> generated.
=========================================================================
* HDL Synthesis *
=========================================================================
Synthesizing Unit <ukladsterujacy>.
Related source file is e:/projekty_vhdl/miroslawcz_proj2/synthesis/./../compile/ukladsterujacy.vhd.
Found finite state machine <FSM_0> for signal <Sreg0>.
-----------------------------------------------------------------------
| States | 10 |
| Transitions | 17 |
| Inputs | 6 |
| Outputs | 4 |
| Clock | clk (rising_edge) |
| Reset | rst (positive) |
| Reset type | asynchronous |
| Reset State | s1 |
| Power Up State | s1 |
| Encoding | automatic |
| Implementation | LUT |
-----------------------------------------------------------------------
Summary:
inferred 1 Finite State Machine(s).
Unit <ukladsterujacy> synthesized.
Synthesizing Unit <ukladoperacyjny>.
Related source file is e:/projekty_vhdl/miroslawcz_proj2/synthesis/./../src/ukladoperacyjny.vhd.
WARNING:Xst:647 - Input <rst> is never used.
WARNING:Xst:643 - The result of a 4x4-bit multiplication found at line 41 is partially used. Only the 7 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
Found 4x4-bit multiplier for signal <$n0000> created at line 41.
Summary:
inferred 1 Multiplier(s).
Unit <ukladoperacyjny> synthesized.
Synthesizing Unit <przetworzenie>.
Related source file is e:/projekty_vhdl/miroslawcz_proj2/synthesis/./../src/przetworzenie.vhd.
Unit <przetworzenie> synthesized.
Synthesizing Unit <calyuklad>.
Related source file is e:/projekty_vhdl/miroslawcz_proj2/synthesis/./../compile/calyuklad.vhd.
WARNING:Xst:1306 - Output <t> is never assigned.
Unit <calyuklad> synthesized.
WARNING:Xst:524 - All outputs of the instance <U1> of the block <przetworzenie> are unconnected in block <calyuklad>.
This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <U2> of the block <ukladoperacyjny> are unconnected in block <calyuklad>.
This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <U3> of the block <ukladsterujacy> are unconnected in block <calyuklad>.
This instance will be removed from the design along with all underlying logic
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
Advanced RAM inference ...
Advanced multiplier inference ...
INFO:Xst:1784 - HDL ADVISOR - Multiplier(s) is(are) identified in your design. You can improve the performance of your multiplier by using the pipeline feature available with mult_style attribute.
Advanced Registered AddSub inference ...
Selecting encoding for FSM_0 ...
Optimizing FSM <FSM_0> on signal <Sreg0> with one-hot encoding.
Dynamic shift register inference ...
=========================================================================
HDL Synthesis Report
Macro Statistics
# FSMs : 1
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
Optimizing unit <calyuklad> ...
Optimizing unit <przetworzenie> ...
Loading device for application Xst from file 'v50.nph' in environment D:/Xilinx.
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block calyuklad, actual ratio is 0.
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : calyuklad.ngr
Top Level Output File Name : calyuklad
Output Format : NGC
Optimization Goal : speed
Keep Hierarchy : no
Design Statistics
# IOs : 19
Cell Usage :
=========================================================================
Device utilization summary:
---------------------------
Selected Device : v50bg256-6
=========================================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
No clock signals found in this design
Timing Summary:
---------------
Speed Grade: -6
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: No path found
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
=========================================================================
CPU : 1.45 / 2.30 s | Elapsed : 1.00 / 2.00 s
-->
Total memory usage is 56440 kilobytes
Processing design ...
Writing file calyuklad.vhd completed.
Synthesis finished with warnings.
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