Low Cost, Low Power
a
Instrumentation Amplifier
AD620
CONNECTION DIAGRAM
FEATURES
EASY TO USE
8-Lead Plastic Mini-DIP (N), Cerdip (Q)
Gain Set with One External Resistor
and SOIC (R) Packages
(Gain Range 1 to 1000)
Wide Power Supply Range ( 2.3 V to 18 V)
8
RG 1 RG
Higher Performance than Three Op Amp IA Designs
Available in 8-Lead DIP and SOIC Packaging IN 2 7 +VS
Low Power, 1.3 mA max Supply Current
+IN 3 6 OUTPUT
EXCELLENT DC PERFORMANCE ( B GRADE )
VS 4 5 REF
AD620
50 V max, Input Offset Voltage
TOP VIEW
0.6 V/ C max, Input Offset Drift
1.0 nA max, Input Bias Current
100 dB min Common-Mode Rejection Ratio (G = 10)
1000. Furthermore, the AD620 features 8-lead SOIC and DIP
packaging that is smaller than discrete designs, and offers lower
LOW NOISE
power (only 1.3 mA max supply current), making it a good fit
9 nV/"Hz, @ 1 kHz, Input Voltage Noise
for battery powered, portable (or remote) applications.
0.28 V p-p Noise (0.1 Hz to 10 Hz)
The AD620, with its high accuracy of 40 ppm maximum
EXCELLENT AC SPECIFICATIONS
nonlinearity, low offset voltage of 50 µV max and offset drift of
120 kHz Bandwidth (G = 100)
0.6 µV/°C max, is ideal for use in precision data acquisition
15 s Settling Time to 0.01%
systems, such as weigh scales and transducer interfaces. Fur-
thermore, the low noise, low input bias current, and low power
APPLICATIONS
of the AD620 make it well suited for medical applications such
Weigh Scales
as ECG and noninvasive blood pressure monitors.
ECG and Medical Instrumentation
Transducer Interface
The low input bias current of 1.0 nA max is made possible with
Data Acquisition Systems
the use of Super²eta processing in the input stage. The AD620
Industrial Process Controls
works well as a preamplifier due to its low input voltage noise of
Battery Powered and Portable Equipment
9 nV/"Hz at 1 kHz, 0.28 µV p-p in the 0.1 Hz to 10 Hz band,
0.1 pA/"Hz input current noise. Also, the AD620 is well suited
PRODUCT DESCRIPTION
for multiplexed applications with its settling time of 15 µs to
The AD620 is a low cost, high accuracy instrumentation ampli-
0.01% and its cost is low enough to enable designs with one in-
fier that requires only one external resistor to set gains of 1 to
amp per channel.
30,000 10,000
25,000
3 OP-AMP
1,000
IN-AMP
(3 OP-07s)
TYPICAL STANDARD
BIPOLAR INPUT
20,000
IN-AMP
100
15,000
G = 100
AD620A
10
10,000
RG
AD620 SUPER ETA
BIPOLAR INPUT
1
IN-AMP
5,000
0 0.1
0 5 10 15 20 1k 10k 100k 1M 10M 100M
SUPPLY CURRENT mA SOURCE RESISTANCE
Figure 1. Three Op Amp IA Designs vs. AD620
Figure 2. Total Voltage Noise vs. Source Resistance
REV. E
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
use, nor for any infringements of patents or other rights of third parties
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
which may result from its use. No license is granted by implication or
Fax: 781/326-8703 © Analog Devices, Inc., 1999
otherwise under any patent or patent rights of Analog Devices.
(0.1 10Hz)
V p-p
RTI VOLTAGE NOISE
TOTAL ERROR, PPM OF FULL SCALE
AD620 SPECIFICATIONS
(Typical @ +25 C, VS = 15 V, and RL = 2 k , unless otherwise noted)
AD620A AD620B AD620S1
Model Conditions Min Typ Max Min Typ Max Min Typ Max Units
GAIN G = 1 + (49.4 k/RG)
Gain Range 1 10,000 1 10,000 1 10,000
Gain Error2 VOUT = Ä… 10 V
G = 1 0.03 0.10 0.01 0.02 0.03 0.10 %
G = 10 0.15 0.30 0.10 0.15 0.15 0.30 %
G = 100 0.15 0.30 0.10 0.15 0.15 0.30 %
G = 1000 0.40 0.70 0.35 0.50 0.40 0.70 %
Nonlinearity, VOUT = 10 V to +10 V,
G = 1 1000 RL = 10 k&! 10 40 10 40 10 40 ppm
G = 1 100 RL = 2 k&! 10 95 10 95 10 95 ppm
Gain vs. Temperature
G =1 10 10 10 ppm/°C
Gain >12 50 50 50 ppm/°C
VOLTAGE OFFSET (Total RTI Error = VOSI + VOSO/G)
Input Offset, VOSI VS = Ä…5 V to Ä…15 V 30 125 15 50 30 125 µV
Over Temperature VS = Ä…5 V to Ä…15 V 185 85 225 µV
Average TC VS = Ä…5 V to Ä…15 V 0.3 1.0 0.1 0.6 0.3 1.0 µV/°C
Output Offset, VOSO VS = Ä…15 V 400 1000 200 500 400 1000 µV
VS = Ä…5 V 1500 750 1500 µV
Over Temperature VS = Ä…5 V to Ä…15 V 2000 1000 2000 µV
Average TC VS = Ä…5 V to Ä…15 V 5.0 15 2.5 7.0 5.0 15 µV/°C
Offset Referred to the
Input vs.
Supply (PSR) VS = Ä…2.3 V to Ä…18 V
G = 1 80 100 80 100 80 100 dB
G = 10 95 120 100 120 95 120 dB
G = 100 110 140 120 140 110 140 dB
G = 1000 110 140 120 140 110 140 dB
INPUT CURRENT
Input Bias Current 0.5 2.0 0.5 1.0 0.5 2 nA
Over Temperature 2.5 1.5 4 nA
Average TC 3.0 3.0 8.0 pA/°C
Input Offset Current 0.3 1.0 0.3 0.5 0.3 1.0 nA
Over Temperature 1.5 0.75 2.0 nA
Average TC 1.5 1.5 8.0 pA/°C
INPUT
Input Impedance
Differential 10 210 210 2G&! pF
Common-Mode 10 210 210 2G&! pF
Input Voltage Range3 VS = Ä…2.3 V to Ä…5 V VS + 1.9 +VS 1.2 VS + 1.9 +VS 1.2 VS + 1.9 +VS 1.2 V
Over Temperature VS + 2.1 +VS 1.3 VS + 2.1 +VS 1.3 VS + 2.1 +VS 1.3 V
VS = Ä…5 V to Ä…18 V VS + 1.9 +VS 1.4 VS + 1.9 +VS 1.4 VS + 1.9 +VS 1.4 V
Over Temperature VS + 2.1 +VS 1.4 VS + 2.1 +VS 1.4 VS + 2.3 +VS 1.4 V
Common-Mode Rejection
Ratio DC to 60 Hz with
I k&! Source Imbalance VCM = 0 V to Ä…10 V
G = 1 73 90 80 90 73 90 dB
G = 10 93 110 100 110 93 110 dB
G = 100 110 130 120 130 110 130 dB
G = 1000 110 130 120 130 110 130 dB
OUTPUT
Output Swing RL = 10 k&!,
VS = Ä…2.3 V to Ä…5 V VS + 1.1 +VS 1.2 VS + 1.1 +VS 1.2 VS + 1.1 +VS 1.2 V
Over Temperature VS + 1.4 +VS 1.3 VS + 1.4 +VS 1.3 VS + 1.6 +VS 1.3 V
VS = Ä…5 V to Ä…18 V VS + 1.2 +VS 1.4 VS + 1.2 +VS 1.4 VS + 1.2 +VS 1.4 V
Over Temperature VS + 1.6 +VS 1.5 VS + 1.6 +VS 1.5 VS + 2.3 +VS 1.5 V
Short Current Circuit Ä… 18 Ä… 18 Ä… 18 mA
2 REV. E
AD620
AD620A AD620B AD620S1
Model Conditions Min Typ Max Min Typ Max Min Typ Max Units
DYNAMIC RESPONSE
Small Signal 3 dB Bandwidth
G = 1 1000 1000 1000 kHz
G = 10 800 800 800 kHz
G = 100 120 120 120 kHz
G = 1000 12 12 12 kHz
Slew Rate 0.75 1.2 0.75 1.2 0.75 1.2 V/µs
Settling Time to 0.01% 10 V Step
G = 1 100 15 15 15 µs
G = 1000 150 150 150 µs
NOISE
Voltage Noise, 1 kHz Total RTI Noise = (e2 )+(eno /G)2
ni
Input, Voltage Noise, eni 9 13 9 13 9 13 nV/"Hz
Output, Voltage Noise, eno 72 100 72 100 72 100 nV/"Hz
RTI, 0.1 Hz to 10 Hz
G = 1 3.0 3.0 6.0 3.0 6.0 µV p-p
G = 10 0.55 0.55 0.8 0.55 0.8 µV p-p
G = 100 1000 0.28 0.28 0.4 0.28 0.4 µV p-p
Current Noise f = 1 kHz 100 100 100 fA/"Hz
0.1 Hz to 10 Hz 10 10 10 pA p-p
REFERENCE INPUT
RIN 20 20 20 k&!
IIN VIN+, VREF = 0 +50 +60 +50 +60 +50 +60 µA
Voltage Range VS + 1.6 +VS 1.6 VS + 1.6 +VS 1.6 VS + 1.6 +VS 1.6 V
Gain to Output 1 Ä… 0.0001 1 Ä… 0.0001 1 Ä… 0.0001
POWER SUPPLY
Operating Range4 Ä… 2.3 Ä…18 Ä…2.3 Ä…18 Ä…2.3 Ä…18 V
Quiescent Current VS = Ä…2.3 V to Ä…18 V 0.9 1.3 0.9 1.3 0.9 1.3 mA
Over Temperature 1.1 1.6 1.1 1.6 1.1 1.6 mA
TEMPERATURE RANGE
For Specified Performance 40 to +85 40 to +85 55 to +125 °C
NOTES
1
See Analog Devices military data sheet for 883B tested specifications.
2
Does not include effects of external resistor RG.
3
One input grounded. G = 1.
4
This is defined as the same supply range which is used to specify PSR.
Specifications subject to change without notice.
REV. E
3
AD620
ABSOLUTE MAXIMUM RATINGS1
ORDERING GUIDE
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ä…18 V
Model Temperature Ranges Package Options*
Internal Power Dissipation2 . . . . . . . . . . . . . . . . . . . . . 650 mW
Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . Ä…VS AD620AN
40°C to +85°C N-8
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . .Ä…25 V
AD620BN 40°C to +85°C N-8
Output Short Circuit Duration . . . . . . . . . . . . . . . . . Indefinite
AD620AR 40°C to +85°C SO-8
Storage Temperature Range (Q) . . . . . . . . . . 65°C to +150°C
AD620AR-REEL 40°C to +85°C 13" REEL
Storage Temperature Range (N, R) . . . . . . . . 65°C to +125°C
AD620AR-REEL7 40°C to +85°C 7" REEL
Operating Temperature Range
AD620BR 40°C to +85°C SO-8
AD620 (A, B) . . . . . . . . . . . . . . . . . . . . . . 40°C to +85°C
AD620BR-REEL 40°C to +85°C 13" REEL
AD620 (S) . . . . . . . . . . . . . . . . . . . . . . . . 55°C to +125°C
AD620BR-REEL7 40°C to +85°C 7" REEL
Lead Temperature Range
AD620ACHIPS 40°C to +85°C Die Form
(Soldering 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . +300°C
AD620SQ/883B 55°C to +125°C Q-8
NOTES
*N = Plastic DIP; Q = Cerdip; SO = Small Outline.
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Specification is for device in free air:
8-Lead Plastic Package: ¸JA = 95°C/W
8-Lead Cerdip Package: ¸JA = 110°C/W
8-Lead SOIC Package: ¸JA = 155°C/W
METALIZATION PHOTOGRAPH
Dimensions shown in inches and (mm).
Contact factory for latest dimensions.
RG* +VS
OUTPUT
8 7 6
5
REFERENCE
8
0.0708
(1.799)
1
4
1 2 3
0.125
VS
RG*
(3.180)
IN +IN
*FOR CHIP APPLICATIONS: THE PADS 1RG AND 8RG MUST BE CONNECTED IN PARALLEL
TO THE EXTERNAL GAIN REGISTER RG. DO NOT CONNECT THEM IN SERIES TO RG. FOR
UNITY GAIN APPLICATIONS WHERE RG IS NOT REQUIRED, THE PADS 1RG MAY SIMPLY
BE BONDED TOGETHER, AS WELL AS THE PADS 8RG.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
WARNING!
accumulate on the human body and test equipment and can discharge without detection.
Although the AD620 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
ESD SENSITIVE DEVICE
precautions are recommended to avoid performance degradation or loss of functionality.
4 REV. E
AD620
(@ +25 C, VS = 15 V, RL = 2 k , unless otherwise noted)
Typical Characteristics
50
2.0
SAMPLE SIZE = 360
1.5
40
1.0
+IB
IB
0.5
30
0
20
0.5
1.0
10
1.5
0
2.0
80 40 0 +40 +80
75 25 25 75 125 175
INPUT OFFSET VOLTAGE V TEMPERATURE C
Figure 3. Typical Distribution of Input Offset Voltage Figure 6. Input Bias Current vs. Temperature
50 2
SAMPLE SIZE = 850
40
1.5
30
1
20
0.5
10
0
0
1200 600 0 +600 +1200
0 1 2 3 4 5
INPUT BIAS CURRENT pA WARM-UP TIME Minutes
Figure 4. Typical Distribution of Input Bias Current Figure 7. Change in Input Offset Voltage vs.
Warm-Up Time
50
1000
SAMPLE SIZE = 850
40
GAIN = 1
100
30
GAIN = 10
20
10
10
GAIN = 100, 1,000
GAIN = 1000
BW LIMIT
0
1
400 200 0 +200 +400
1 10 100 1k 10k 100k
INPUT OFFSET CURRENT pA FREQUENCY Hz
Figure 5. Typical Distribution of Input Offset Current Figure 8. Voltage Noise Spectral Density vs. Frequency,
(G = 1 1000)
REV. E 5
PERCENTAGE OF UNITS
INPUT BIAS CURRENT nA
PERCENTAGE OF UNITS
CHANGE IN OFFSET VOLTAGE
V
PERCENTAGE OF UNITS
VOLTAGE NOISE nV/
Hz
AD620 Typical Characteristics
1000
100
10
1 10 100 1000
FREQUENCY Hz
Figure 9. Current Noise Spectral Density vs. Frequency Figure 11. 0.1 Hz to 10 Hz Current Noise, 5 pA/Div
100,000
10,000
FET INPUT
IN-AMP
1000
AD620A
100
10
TIME 1 SEC/DIV
1k 10k 100k 1M 10M
SOURCE RESISTANCE
Figure 12. Total Drift vs. Source Resistance
Figure 10a. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1)
+160
G = 1000
+140
G = 100
+120
G = 10
+100
G = 1
+80
+60
+40
+20
0
0.1 1 10 100 1k 10k 100k 1M
TIME 1 SEC/DIV
FREQUENCY Hz
Figure 13. CMR vs. Frequency, RTI, Zero to 1 k&! Source
Figure 10b. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1000)
Imbalance
6 REV. E
CURRENT NOISE fA/
Hz
RTI NOISE 2.0
V/DIV
TOTAL DRIFT FROM 25
C TO 85
C, RTI
V
CMR dB
RTI NOISE 0.1
V/DIV
AD620
180 35
G = 10, 100, 1000
160
30
140
25
G = 1000
120
G = 1
20
100
G = 100
15
80
G = 10
10
60
G = 1
5
40
G = 1000
G = 100
20 0
0.1 1 10 100 1k 10k 100k 1M 1k 10k 100k 1M
FREQUENCY Hz FREQUENCY Hz
Figure 17. Large Signal Frequency Response
Figure 14. Positive PSR vs. Frequency, RTI (G = 1 1000)
+VS 0.0
180
160 0.5
1.0
140
1.5
120
100
G = 1000
80 +1.5
G = 100
60 +1.0
G = 10
40 +0.5
G = 1
20 VS +0.0
0 5 10 15 20
0.1 1 10 100 1k 10k 100k 1M
SUPPLY VOLTAGE Volts
FREQUENCY Hz
Figure 15. Negative PSR vs. Frequency, RTI (G = 1 1000)
Figure 18. Input Voltage Range vs. Supply Voltage, G = 1
1000
+VS 0.0
0.5
RL = 10k
1.0
100
RL = 2k
1.5
10
+1.5
RL = 2k
+1.0
1
RL = 10k
+0.5
VS +0.0
0.1
100 1k 10k 100k 1M 10M 5 10 15 20
0
FREQUENCY Hz
SUPPLY VOLTAGE Volts
Figure 16. Gain vs. Frequency Figure 19. Output Voltage Swing vs. Supply Voltage,
G = 10
REV. E 7
PSR dB
BW LIMIT
OUTPUT VOLTAGE Volts p-p
PSR dB
INPUT VOLTAGE LIMIT Volts
(REFERRED TO SUPPLY VOLTAGES)
GAIN V/V
OUTPUT VOLTAGE SWING Volts
(REFERRED TO SUPPLY VOLTAGES)
AD620
30
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VS = 15V
G = 10
20
10
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0
0 100 1k 10k
LOAD RESISTANCE
Figure 20. Output Voltage Swing vs. Load Resistance
Figure 23. Large Signal Response and Settling Time,
G = 10 (0.5 mV = 001%)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 21. Large Signal Pulse Response and Settling Time Figure 24. Small Signal Response, G = 10, RL = 2 k&!,
G = 1 (0.5 mV = 0.01%) CL = 100 pF
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 22. Small Signal Response, G = 1, RL = 2 k&!, Figure 25. Large Signal Response and Settling Time,
CL = 100 pF G = 100 (0.5 mV = 0.01%)
8 REV. E
OUTPUT VOLTAGE SWING Volts p-p
AD620
20
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
TO 0.01%
TO 0.1%
10
5
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0
020
5 10 15
OUTPUT STEP SIZE Volts
Figure 26. Small Signal Pulse Response, G = 100, Figure 29. Settling Time vs. Step Size (G = 1)
RL = 2 k&!, CL = 100 pF
1000
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
100
10
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
1 10 100 1000
GAIN
Figure 27. Large Signal Response and Settling Time, Figure 30. Settling Time to 0.01% vs. Gain, for a 10 V Step
G = 1000 (0.5 mV = 0.01%)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 28. Small Signal Pulse Response, G = 1000,
Figure 31a. Gain Nonlinearity, G = 1, RL = 10 k&!
RL = 2 k&!, CL = 100 pF
(10 µV = 1 ppm)
REV. E 9
SETTLING TIME
s
SETTLING TIME
s
AD620
20 A VB
I1 20 A I2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A1 A2
10k
C1 C2
10k
A3 OUTPUT
10k 10k
R3
R1 R2 REF
400
IN Q1 Q2 +IN
R4
RG
400
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GAIN GAIN
SENSE SENSE
VS
Figure 33. Simplified Schematic of AD620
Figure 31b. Gain Nonlinearity, G = 100, RL = 10 k&!
(100 µV = 10 ppm)
THEORY OF OPERATION
The AD620 is a monolithic instrumentation amplifier based on
a modification of the classic three op amp approach. Absolute
value trimming allows the user to program gain accurately (to
0.15% at G = 100) with only one resistor. Monolithic construc-
tion and laser wafer trimming allow the tight matching and
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
tracking of circuit components, thus ensuring the high level of
performance inherent in this circuit.
The input transistors Q1 and Q2 provide a single differential-
pair bipolar input for high precision (Figure 33), yet offer 10×
lower Input Bias Current thanks to Super²eta processing. Feed-
back through the Q1-A1-R1 loop and the Q2-A2-R2 loop main-
tains constant collector current of the input devices Q1, Q2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
thereby impressing the input voltage across the external gain
setting resistor RG. This creates a differential gain from the
inputs to the A1/A2 outputs given by G = (R1 + R2)/RG + 1.
The unity-gain subtracter A3 removes any common-mode sig-
nal, yielding a single-ended output referred to the REF pin
potential.
Figure 31c. Gain Nonlinearity, G = 1000, RL = 10 k&!
The value of RG also determines the transconductance of the
(1 mV = 100 ppm)
preamp stage. As RG is reduced for larger gains, the transcon-
ductance increases asymptotically to that of the input transistors.
1k
This has three important advantages: (a) Open-loop gain is
10k * 10k
10T
INPUT
boosted for increasing programmed gain, thus reducing gain-
10V p-p
100k
related errors. (b) The gain-bandwidth product (determined by
VOUT
C1, C2 and the preamp transconductance) increases with pro-
grammed gain, thus optimizing frequency response. (c) The
+VS
input voltage noise is reduced to a value of 9 nV/"Hz, deter-
2
11k 1k 100
mined mainly by the collector current and base resistance of the
7
1
input devices.
G=1000
G=1
The internal gain resistors, R1 and R2, are trimmed to an abso-
AD620
6
G=10
G=100
lute value of 24.7 k&!, allowing the gain to be programmed
49.9 499 5.49k
5
accurately with a single external resistor.
8
4
The gain equation is then
3
VS
49.4 k&!
G = + 1
*ALL RESISTORS 1% TOLERANCE
RG
Figure 32. Settling Time Test Circuit
so that
49.4 k&!
RG =
G - 1
10 REV. E
AD620
Make vs. Buy: A Typical Bridge Application Error Budget systems, absolute accuracy and drift errors are by far the most
The AD620 offers improved performance over homebrew significant contributors to error. In more complex systems with
three op amp IA designs, along with smaller size, fewer compo- an intelligent processor, an autogain/autozero cycle will remove all
nents and 10× lower supply current. In the typical application, absolute accuracy and drift errors leaving only the resolution
shown in Figure 34, a gain of 100 is required to amplify a bridge errors of gain nonlinearity and noise, thus allowing full 14-bit
output of 20 mV full scale over the industrial temperature range accuracy.
of 40°C to +85°C. The error budget table below shows how to
Note that for the homebrew circuit, the OP07 specifications for
calculate the effect various error sources have on circuit accuracy.
input voltage offset and noise have been multiplied by "2. This
Regardless of the system in which it is being used, the AD620 is because a three op amp type in-amp has two op amps at its
provides greater accuracy, and at low power and price. In simple inputs, both contributing to the overall input error.
+10V
10k * 10k *
OP07D
R = 350 R = 350
10k **
RG
AD620A
499 100 **
OP07D
10k **
R = 350 R = 350
REFERENCE
OP07D
10k * 10k *
AD620A MONOLITHIC
PRECISION BRIDGE TRANSDUCER HOMEBREW IN-AMP, G = 100
INSTRUMENTATION
*0.02% RESISTOR MATCH, 3PPM/ C TRACKING
AMPLIFIER, G = 100
**DISCRETE 1% RESISTOR, 100PPM/ C TRACKING
SUPPLY CURRENT = 15mA MAX
SUPPLY CURRENT = 1.3mA MAX
Figure 34. Make vs. Buy
Table I. Make vs. Buy Error Budget
AD620 Circuit Homebrew Circuit Error, ppm of Full Scale
Error Source Calculation Calculation AD620 Homebrew
ABSOLUTE ACCURACY at TA = +25°C
Input Offset Voltage, µV 125 µV/20 mV (150 µV × "2)/20 mV 16,250 10,607
Output Offset Voltage, µV 1000 µV/100/20 mV ((150 µV × 2)/100)/20 mV 14,500 10,150
Input Offset Current, nA 2 nA × 350 &!/20 mV (6 nA × 350 &!)/20 mV 14,118 14,153
CMR, dB 110 dB3.16 ppm, × 5 V/20 mV (0.02% Match × 5 V)/20 mV/100 14,791 10,500
Total Absolute Error 17,558 11,310
DRIFT TO +85°C
Gain Drift, ppm/°C (50 ppm + 10 ppm) × 60°C 100 ppm/°C Track × 60°C 13,600 16,000
Input Offset Voltage Drift, µV/°C 1 µV/°C × 60°C/20 mV (2.5 µV/°C × "2 × 60°C)/20 mV 13,000 10,607
Output Offset Voltage Drift, µV/°C 15 µV/°C × 60°C/100/20 mV (2.5 µV/°C × 2 × 60°C)/100/20 mV 14,450 10,150
Total Drift Error 17,050 16,757
RESOLUTION
Gain Nonlinearity, ppm of Full Scale 40 ppm 40 ppm 14,140 10,140
Typ 0.1 Hz 10 Hz Voltage Noise, µV p-p 0.28 µV p-p/20 mV (0.38 µV p-p × "2)/20 mV 141,14 13,127
Total Resolution Error 14,154 101,67
Grand Total Error 14,662 28,134
G = 100, VS = Ä…15 V.
(All errors are min/max and referred to input.)
REV. E 11
AD620
+5V
20k
7
3
3k 3k
REF
8
G=100 6 IN
AD620B
DIGITAL
499
3k 3k
5
10k DATA
ADC
1
OUTPUT
2 4
AD705 AGND
20k
0.6mA
1.7mA 0.10mA
1.3mA
MAX
MAX
Figure 35. A Pressure Monitor Circuit which Operates on a +5 V Single Supply
Pressure Measurement Medical ECG
Although useful in many bridge applications such as weigh The low current noise of the AD620 allows its use in ECG
scales, the AD620 is especially suitable for higher resistance monitors (Figure 36) where high source resistances of 1 M&! or
pressure sensors powered at lower voltages where small size and higher are not uncommon. The AD620 s low power, low supply
low power become more significant. voltage requirements, and space-saving 8-lead mini-DIP and
SOIC package offerings make it an excellent choice for battery
Figure 35 shows a 3 k&! pressure transducer bridge powered
powered data recorders.
from +5 V. In such a circuit, the bridge consumes only 1.7 mA.
Adding the AD620 and a buffered voltage divider allows the Furthermore, the low bias currents and low current noise
signal to be conditioned for only 3.8 mA of total supply current. coupled with the low voltage noise of the AD620 improve the
dynamic range for better performance.
Small size and low cost make the AD620 especially attractive for
voltage output pressure transducers. Since it delivers low noise The value of capacitor C1 is chosen to maintain stability of the
and drift, it will also serve applications such as diagnostic non- right leg drive loop. Proper safeguards, such as isolation, must
invasive blood pressure measurement. be added to this circuit to protect the patient from possible
harm.
+3V
PATIENT/CIRCUIT
PROTECTION/ISOLATION
R1 R3
0.03Hz
C1 24.9k
10k
RG HIGH OUTPUT
AD620A
G = 143
8.25k PASS 1V/mV
R4 R2 FILTER
G = 7
24.9k
1M
OUTPUT
AMPLIFIER
AD705J
3V
Figure 36. A Medical ECG Monitor Circuit
12 REV. E
AD620
Precision V-I Converter
INPUT AND OUTPUT OFFSET VOLTAGE
The AD620, along with another op amp and two resistors, makes
The low errors of the AD620 are attributed to two sources,
a precision current source (Figure 37). The op amp buffers the
input and output errors. The output error is divided by G when
reference terminal to maintain good CMR. The output voltage
referred to the input. In practice, the input errors dominate at
VX of the AD620 appears across R1, which converts it to a
high gains and the output errors dominate at low gains. The
current. This current less only, the input bias current of the op
total VOS for a given gain is calculated as:
amp, then flows out to the load.
Total Error RTI = input error + (output error/G)
+VS Total Error RTO = (input error × G) + output error
7
VIN+ REFERENCE TERMINAL
3
The reference terminal potential defines the zero output voltage,
8
+ V
X
and is especially useful when the load does not share a precise
RG
AD620 6
R1
ground with the rest of the system. It provides a direct means of
1
5
injecting a precise offset to the output, with an allowable range
VIN
2
4
IL
of 2 V within the supply voltages. Parasitic resistance should be
kept to a minimum for optimum CMR.
VS
AD705
[(VIN+) (VIN )] G INPUT PROTECTION
Vx
I = =
L
R1 R1
The AD620 features 400 &! of series thin film resistance at its
LOAD
inputs, and will safely withstand input overloads of up to Ä…15 V
or Ä…60 mA for several hours. This is true for all gains, and power
Figure 37. Precision Voltage-to-Current Converter
on and off, which is particularly important since the signal
(Operates on 1.8 mA, Ä…3 V)
source and amplifier may be powered separately. For longer
time periods, the current should not exceed 6 mA (IIN d"
GAIN SELECTION
VIN/400 &!). For input overloads beyond the supplies, clamping
The AD620 s gain is resistor programmed by RG, or more pre- the inputs to the supplies (using a low leakage diode such as an
cisely, by whatever impedance appears between Pins 1 and 8.
FD333) will reduce the required resistance, yielding lower
The AD620 is designed to offer accurate gains using 0.1% 1%
noise.
resistors. Table II shows required values of RG for various gains.
Note that for G = 1, the RG pins are unconnected (RG = "). For
RF INTERFERENCE
any arbitrary gain RG can be calculated by using the formula:
All instrumentation amplifiers can rectify out of band signals,
and when amplifying small signals, these rectified voltages act as
49.4 k&!
small dc offset errors. The AD620 allows direct access to the
RG =
G - 1
input transistor bases and emitters enabling the user to apply
some first order filtering to unwanted RF signals (Figure 38),
To minimize gain error, avoid high parasitic resistance in series
where RC 1/(2 Ä„f) and where f e" the bandwidth of the
with RG; to minimize gain drift, RG should have a low TC less
AD620; C d" 150 pF. Matching the extraneous capacitance at
than 10 ppm/°C for the best performance.
Pins 1 and 8 and Pins 2 and 3 helps to maintain high CMR.
Table II. Required Values of Gain Resistors
RG
1% Std Table Calculated 0.1% Std Table Calculated
Value of RG, Gain Value of RG, Gain
1
8
49.9 k 1.990 49.3 k 2.002
C
12.4 k 4.984 12.4 k 4.984
R
2
IN 7
5.49 k 9.998 5.49 k 9.998
R
2.61 k 19.93 2.61 k 19.93
+IN 3
6
1.00 k 50.40 1.01 k 49.91
499 100.0 499 100.0
4
5
249 199.4 249 199.4
C
100 495.0 98.8 501.0
49.9 991.0 49.3 1,003
Figure 38. Circuit to Attenuate RF Interference
REV. E 13
AD620
COMMON-MODE REJECTION GROUNDING
Instrumentation amplifiers like the AD620 offer high CMR, Since the AD620 output voltage is developed with respect to the
which is a measure of the change in output voltage when both potential on the reference terminal, it can solve many grounding
inputs are changed by equal amounts. These specifications are problems by simply tying the REF pin to the appropriate local
usually given for a full-range input voltage change and a speci- ground.
fied source imbalance.
In order to isolate low level analog signals from a noisy digital
For optimal CMR the reference terminal should be tied to a low environment, many data-acquisition components have separate
impedance point, and differences in capacitance and resistance analog and digital ground pins (Figure 41). It would be conve-
should be kept to a minimum between the two inputs. In many nient to use a single ground line; however, current through
applications shielded cables are used to minimize noise, and for ground wires and PC runs of the circuit card can cause hun-
best CMR over frequency the shield should be properly driven. dreds of millivolts of error. Therefore, separate ground returns
Figures 39 and 40 show active data guards that are configured should be provided to minimize the current flow from the sensi-
to improve ac common-mode rejections by bootstrapping the tive points to the system ground. These ground returns must be
capacitances of input cable shields, thus minimizing the capaci- tied together at some point, usually best at the ADC package as
tance mismatch between the inputs. shown.
+VS
ANALOG P.S. DIGITAL P.S.
INPUT
+15V C 15V C +5V
AD648
100
0.1 F
0.1 F
1 F 1 F 1 F
AD620
VOUT
RG
+
100
VS
AD620
DIGITAL
AD585
REFERENCE AD574A
DATA
S/H ADC
OUTPUT
+ INPUT
VS
Figure 41. Basic Grounding Practice
Figure 39. Differential Shield Driver
+VS
INPUT
RG
2
100
AD620
VOUT
AD548
RG
2
REFERENCE
+ INPUT
VS
Figure 40. Common-Mode Shield Driver
14 REV. E
AD620
GROUND RETURNS FOR INPUT BIAS CURRENTS sources such as transformers, or ac-coupled sources, there must
Input bias currents are those currents necessary to bias the input be a dc path from each input to ground as shown in Figure 42.
transistors of an amplifier. There must be a direct return path Refer to the Instrumentation Amplifier Application Guide (free
for these currents; therefore, when amplifying floating input from Analog Devices) for more information regarding in amp
applications.
+VS
+VS
INPUT
INPUT
RG
VOUT
AD620 VOUT AD620
RG
LOAD
LOAD
REFERENCE
+ INPUT REFERENCE + INPUT
VS
VS
TO POWER
TO POWER
SUPPLY
SUPPLY
GROUND
GROUND
Figure 42b. Ground Returns for Bias Currents with
Figure 42a. Ground Returns for Bias Currents with
Thermocouple Inputs
Transformer Coupled Inputs
+VS
INPUT
VOUT
RG AD620
LOAD
+ INPUT REFERENCE
VS
100k 100k
TO POWER
SUPPLY
GROUND
Figure 42c. Ground Returns for Bias Currents with AC Coupled Inputs
REV. E 15
AD620
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Plastic DIP (N-8) Package
0.430 (10.92)
0.348 (8.84)
8 5
0.280 (7.11)
0.240 (6.10)
1 4
0.325 (8.25)
0.300 (7.62)
0.060 (1.52)
PIN 1
0.015 (0.38)
0.195 (4.95)
0.210 (5.33)
0.115 (2.93)
MAX
0.130
0.160 (4.06) (3.30)
MIN
0.115 (2.93)
0.015 (0.381)
SEATING
0.022 (0.558) 0.100 0.070 (1.77)
0.008 (0.204)
PLANE
(2.54)
0.014 (0.356) 0.045 (1.15)
BSC
Cerdip (Q-8) Package
0.005 (0.13) 0.055 (1.4)
MIN MAX
8 5
0.310 (7.87)
0.220 (5.59)
1 4
PIN 1
0.320 (8.13)
0.405 (10.29)
0.290 (7.37)
0.060 (1.52)
MAX
0.015 (0.38)
0.200 (5.08)
MAX
0.150
(3.81)
0.200 (5.08)
MIN
0.125 (3.18)
0.015 (0.38)
SEATING
0.023 (0.58) 0.100 0.070 (1.78)
15°
0.008 (0.20)
PLANE
(2.54)
0.014 (0.36) 0.030 (0.76) 0°
BSC
SOIC (SO-8) Package
0.1968 (5.00)
0.1890 (4.80)
8 5
0.1574 (4.00) 0.2440 (6.20)
1 4
0.1497 (3.80) 0.2284 (5.80)
PIN 1 0.0688 (1.75)
0.0196 (0.50)
x 45°
0.0098 (0.25) 0.0532 (1.35)
0.0099 (0.25)
0.0040 (0.10)
8°
0.0500 0.0192 (0.49)
0°
SEATING 0.0098 (0.25) 0.0500 (1.27)
(1.27)
0.0138 (0.35)
PLANE
BSC 0.0075 (0.19) 0.0160 (0.41)
16 REV. E
C1599c 0 7/99
PRINTED IN U.S.A.
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