CXD2500BQ
CD Digital Signal Processor
Description
80 pin QFP (Plastic)
The CXD2500BQ is a digital signal processing LSI
designed for use in compact disc players. It has the
following functions:
" Wide-frame jitter margin (Ä…28 frames) realized by a
built-in 32K RAM.
" Bit clock generated by digital PLL for strobing EFM
signals. Capture range of Ä…150 kHz and over.
" EFM data demodulation
" Enhanced protection of EFM Frame Sync signals
" Powerful error correction based on Refined Super
Strategy
Error correction C1: Double correction
C2: Quadruple correction
" Double-speed playback and vari-pitch playback
" Reduced noise generation at track jump
" Auto zero-cross muting
" Subcode demodulation and subcode Q data error
detection
" Digital spindle servo system (incorporating an
oversampling filter)
" 16-bit traverse counter
" Built-in asymmetry correction circuit
" CPU interface using a serial bus
" Servo auto sequencer
" Output for digital audio interface
" Built-in digital level meter and peak meter
" Bilingual
Features
" All digital signals for regeneration are processed
using one chip.
" The built-in RAM enables high-integration
mounting.
Structure
Silicon-gate CMOS IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
 1
E91Y46F64-TE
CXD2500BQ
Absolute Maximum Ratings (Ta=25 °C)
" Supply voltage VCC  0.3 to +7.0 V
" Input voltage VI  0.3 to +7.0 V
" Output voltage VO  0.3 to +7.0 V
" Operating temperature Topr  20 to +75 °C
" Storage temperature Tstg  40 to +125 °C
" Supply voltage differences VSS AVSS  0.3 to +0.3 V
VDD AVDD  0.3 to +0.3 V
Recommended Operating Conditions
" Supply voltage VDD 4.75" 1 to 5.25" 3 (5.0 V typ.) V
" Operating temperature Topr  20 to +75 °C
" Input voltage VIN VSS 0.3 to + VDD + 0.3 V
" 1
VDD value of 4.75 V (min.) is for the double-speed playback mode at vari-pitch control reset. For the low
" 2
power consumption special playback mode, VDD value is 3.6 V (min.). In the normal-speed playback
mode VDD value is 4.5 V (min.)
" 2
Low power consumption, special playback mode
Set the internal operation of LSI at the double-speed mode, and half the crystal oscillation frequency. This
will result in the normal-speed playback mode.
" 3
VDD value of 5.25 V (max.) is for the double-speed playback mode at vari-pitch control reset. For normal-
speed playback and the low power consumption special playback mode, the VDD value is 5.5 V (max.).
I/O Capacity
" Input pins CI 12 pF max.
" Output pins CO 12 pF max. at high impedance
Note: Test Conditions
VDD=VI=0 V
fM=1 MHz
 2
CXD2500BQ
Block Diagram
56 53 54 53 17 19
57 23
C4M AVDD
Clock
58 21
C16M AVSS
generator
32K RAM
11 33
PDO VDD
73
VCO1 VDD
9
Digital PLL
EFM
vari-pitch 12
VCO0 VSS
8 demodulator
double speed
Address Priority
20 generator encoder 52
PCO VSS
19
FIL1
8
18
FIL0
Sync
30
PSSL
Protector
22
CLTV
49
D/A DAO 1 to 6
24 data processor
RF
26
ASY1 " MUX
MUTE
68
27
ASY0
28
ASYE
Timing
62
WFCK Peak detector
Generator
63
SCOR
Digital out
60
EXCK 65 Subcode DOUT
P-W
Processor
SBSO 64
MD 2
59
EMPH 61
71
DATA
Error corrector
SQCK 67
Subcode
74
CPU interface CLOK
Q
Processor
SQSO 66
72 XLAT
MON
3
FSW
CLV
2
processor
MDP
4
77 DATO
MDS 43
Servo
Timing
auto 79 CLKO
Generator 2
sequencer
78
XLTO
18-times
Noise
over samplling
TEST 10 shaper
filter
NC
5
"Asymmetry
correction.
70 50 51 32 31 75 69 76 80
6 1
 3
VPCO
XTAO
XTSL
VCKI
FSTT
XTAI
Register
processor
Serial/Parallel
FOX
SEIN
CNIN
APTL
MIRR
LRCK
XRST
APTR
LOCK
SENS
WDCK
CXD2500BQ
Pin Configuration
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
65 40
EXCK DA10
66 39
SQSO DA11
67 38
SQCK DA12
68 37
MUTE DA13
69 36
SENS DA14
70 35
XRST DA15
71 34
DATA DA16
72 33
XLAT VDD
D2500B
73 32
VDD LRCK
74 31
CLOK WDCK
75 30
SEIN PSSL
76 29 NC
CNIN
77 28
DATO ASYE
78 27
XLTO ASYO
79 26
CLKO ASYI
80 25
MIRR BIAS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
 4
FSTT
XTAQ
V
SS
XTSL
APTR
XTAI
DA02
APLL
DA04
DA01
DA06
DA03
DA08
DA05
SBSO
DA07
WFCK
C4M
C16M
SCOR
DOUT
MD2
DA09
EMPH
RF
NC
NC
NC
NC
FILI
V
SS
FOK
PDO
MDS
PCO
FSW
MDP
FILO
MON
VCKI
AV
SS
AV
DD
VCOI
TEST
CLTV
LOCK
VPCO
VCOO
CXD2500BQ
Pin Description
Pin
Symbol I/O Description
No.
1 FOK I Focus OK input. Used for SENS output and servo auto sequencer.
2 FSW O Z, 0 Output used to switch the spindle motor output filter.
3 MON O 1, 0 Output for spindle motor ON/OFF control
4 MDP O 1, Z, 0 Output for spindle motor servo control
5 MDS O 1, Z, 0 Output for spindle motor servo control
Output is  H when the GFS signal sampled at 460 Hz is  H . Output is
6 LOCK O 1, 0
 L when the GFS signal is  L 8 or more times in succession.
7 NC 
8 VCOO O 1, 0 Output of oscillation circuit for analog EFM PLL
9 VCOI I Input to oscillation circuit for analog EFM PLL fLOCK=8.6436 MHz
10 TEST I Test. Normally at 0 V (GND).
11 PDO O 1, Z, 0 Output of charge pump for analog EFM PLL
12 VSS GND
13 NC 
14 NC 
15 NC 
16 VPCO O 1, Z, 0 Output of charge pump for vari-pitch PLL
17 VCKI I Clock input from external VCO for vari-pitch control. fc center=16.9344 MHz.
18 FILO O Analog Output of filter for master PLL (Slave=Digital PLL)
19 FILI I Input to filter for master PLL
20 PCO O 1, Z, 0 Output of charge pump for master PLL
21 AVSS Analog GND
22 CLTV I VCO control voltage input for master PLL
23 AVDD Analog power supply (+5 V)
24 RF I EFM signal input
25 BIAS I Asymmetry circuit constant current input
26 ASYI I Asymmetry comparator circuit voltage input
27 ASYO O 1, 0 EFM full-swing output
28 ASYE I Asymmetry circuit OFF at  L . Asymmetry circuit ON at  H .
29 NC 
Input used to switch the audio data output mode.  L for serial output,
30 PSSL I
 H for parallel output.
31 WDCK O 1, 0 D/A interface for 48-bit slot. Word clock f=2Fs
32 LRCK O 1, 0 D/A interface for 48-bit slot. LR clock f=Fs
33 VDD Power supply (+5 V)
Outputs DA16 (MSB) when PSSL=1, or serial data from the 48-bit slot
34 DA16 O 1, 0
(2 s complements, MSB first) when PSSL=0.
35 DA15 O 1, 0 Outputs DA15 when PSSL=1, or bit clock from the 48-bit slot when PSSL=0.
Outputs DA14 when PSSL=1, or serial data from the 64-bit slot (2 s
36 DA14 O 1, 0
complements, LSB first) when PSSL=0.
37 DA13 O 1, 0 Outputs DA13 when PSSL=1, or bit clock from the 64-bit slot when PSSL=0.
38 DA12 O 1, 0 Outputs DA12 when PSSL=1, or LR clock from the 64-bit slot when PSSL=0.
39 DA11 O 1, 0 Outputs DA11 when PSSL=1, or GTOP when PSSL=0.
40 DA10 O 1, 0 Outputs DA10 when PSSL=1, or XUGF when PSSL=0.
 5
CXD2500BQ
Pin
Symbol I/O Description
No.
41 DA09 O 1, 0 Outputs DA9 when PSSL=1, or XPLCK when PSSL=0.
42 DA08 O 1, 0 Outputs DA8 when PSSL=1, or GFS when PSSL=0.
43 DA07 O 1, 0 Outputs DA7 when PSSL=1, or RFCK when PSSL=0.
44 DA06 O 1, 0 Outputs DA6 when PSSL=1, or C2PO when PSSL=0.
45 DA05 O 1, 0 Outputs DA5 when PSSL=1, or XRAOF when PSSL=0.
46 DA04 O 1, 0 Outputs DA4 when PSSL=1, or MNT3 when PSSL=0.
47 DA03 O 1, 0 Outputs DA3 when PSSL=1, or MNT2 when PSSL=0.
48 DA02 O 1, 0 Outputs DA2 when PSSL=1, or MNT1 when PSSL=0.
49 DA01 O 1, 0 Outputs DA1 when PSSL=1, or MNT0 when PSSL=0.
50 APTR O 1, 0 Control output for aperture correction.  H for R-ch.
51 APTL O 1, 0 Control output for aperture correction.  H for L-ch.
52 VSS GND
53 XTAI I Input for 16.9344 MHz and 33.8688 MHz X'tal oscillation circuit.
54 XTAO O 1, 0 Output for 16.9344 MHz X'tal oscillation circuit.
55 XTSL I X'tal selection input.  L for 16.9344 MHz X'tal,  H for 33.8688 MHz X'tal.
2/3 frequency demultiplication output for Pins 53 and 54. Unaffected by
56 FSTT O 1, 0
vari-pitch control.
57 C4M O 1, 0 4.2336 MHz output. Subject to vari-pitch control.
58 C16M O 1, 0 16.9344 MHz output. Subject to vari-pitch control.
59 MD2 I Digital-Out ON/OFF control.  H for ON,  L for OFF.
60 DOUT O 1, 0 Digital-Out output.
61 EMPH O 1, 0  H for playback disc provided with emphasis,  L for without emphasis.
62 WFCK O 1, 0 WFCK (Write Frame Clock) output.
63 SCOR O 1, 0  H when subcode Sync S0 or S1 is detected.
64 SBSO O 1, 0 Serial output of Sub P to W
65 EXCK I Clock input for reading SBSO
66 SQSO O 1, 0 Outputs 80-bit Sub Q and 16-bit PCM peak-level data.
67 SQCK I Clock input for reading SQSO
68 MUTE I  H for muting,  L for release.
69 SENS  1, Z, 0 SENS output to CPU
70 XRST I System reset.  L for resetting.
71 DATA I Inputs serial data from CPU.
72 XLAT I Latches serial data input from CPU at falling edge.
73 VDD Power supply (+5 V)
74 CLOCK I Inputs serial data transfer clock from CPU.
75 SEIN I Inputs SENSE from SSP.
76 CNIN I Inputs track jump count signal.
77 DATO O 1, 0 Outputs serial data to SSP.
78 XLTO O 1, 0 Latches serial data output to SSP at falling edge.
79 CLKO O 1, 0 Outputs serial data transfer clock to SSP.
Inputs mirror signal to be used by auto sequencer when jumping 16 or
80 MIRR I
more tracks.
 6
CXD2500BQ
Note:
" The data at the 64-bit slot is output in 2 s complements on an LSB-first basis. The data at the 48-bit slot is
output in 2 s complements on an MSB-first basis.
" GTOP monitors the state of Frame Sync protection. ( H : Sync protection window released)
" XUFG is a negative Frame Sync pulse obtained from the EFM signal before Frame Sync protection is
effected..
" XPLCK is an inversion of the EFM PLL clock. The PLL is designed so that the falling edge of XPLCK
coincides with a change point of the EFM signal.
" The GFS signal turns  H upon coincidence between Frame Sync and the timing of interpolation protection.
" RFCK is a signal generated at 136-µs periods using a crystal oscillator.
" C2PO is a signal to indicate data error.
" XRAOF is a signal issued when a jitter margin of Ä…28F is exceeded by the 32K RAM.
 7
CXD2500BQ
Electrical Character
DC characteristics (VDD=AVDD=5.0 VÄ…5 %, VSS=AVSS=0 V, Topr= 20 to +75°C)
Item Condition Min. Typ. Max. Unit Related pins
Input voltage.
VIH (1) 0.7VDD V
 H level
" 1
Input voltage
VIL (1) 0.3VDD V
 L level.
Input voltage
VIN (2) 0.8VDD V
 H level Schmitt circuit
" 2
Input voltage input
VIN (2) 0.2VDD V
 L level
Input voltage VIN (3) Analog input VSS VDD V " 3
Output voltage
VOH (1) IOH= 1 mA VDD 0.5 VDD V
 H level
" 4
Output voltage
VOL (1) IOL=1 mA 0 0.4 V
 L level
Output voltage
VOH (2) IOH= 1 mA VDD 0.5 VDD V
 H level
" 5
Output voltage
VOL (2) IOL=2 mA 0 0.4 V
 L level
Output voltage
"
VOL (3) IOL=2 mA 0 0.4 V 6
 L level
Output voltage
VOH (4) IOH= 0.28 mA VDD 0.5 VDD V
 H level
"
7
Output voltage
VOL (4) IOL=0.36 mA 0 0.4 V
 L level
"
Input leak current ILI VI=0 to 5.25 V Ä…5 µA 1, " 2, " 3
Tristate pin output leak
"
ILO VO=0 to 5.25 V Ä…5 µA 8
current
Related pins
"
1 XTSL, DATA, XLAT, MD2, PSSL
"
2 CLOK, XRST, EXCK, SQCK, MUTE, FOK, SEIN, CNIN, MIRR, VCKI, ASYE
"
3 CLTV, FILI, RF
"
4 MDP, PDO, PCO, VPCO
"
5 ASYO, DOUT, FSTT, C4M, C16M, SBSO, SQSO, SCOR, EMPH, MON, LOCK, WDCK, DATO, CLKO,
XLTO, SENS, MDS, DA01 to DA16, APTR, APTL, LRCK, WFCK
"
6 FSW
"
7 FILO
"
8 SENS, MDS, MDP, FSW, PDO, PCO, VPCO
 8
Input
Output
Output
Output
Output
Input
Input
voltage (4)
voltage (3)
voltage (2)
voltage (1)
voltage (3)
voltage (2)
voltage (1)
CXD2500BQ
AC Characteristics
(1) XTAI and VCOI pins
1) During self-oscillation (Topr= 20 to +75 °C, VDD=AVDD=5.0 VÄ…5 %)
Item Symbol Min. Typ. Max. Unit
Oscillation frequency fMAX 7 34 MHz
2) With pulses input to XTAI and VCOI pins (Topr= 20 to +75 °C, VDD=AVDD=5.0 VÄ…5 %)
Item Symbol Min. Typ. Max. Unit
 H level pulse width tWHX 13 500
 L level pulse width tWLX 13 500 ns
Pulse period tCX 26 1,000
Input  H level VIHX VDD 1.0
V
Input  L level VILX 0.8
Rising time
tR, tF 10 ns
Falling time
tCX
tWHX tWLX
VIHX
VIHX×0.9
VDD/2
XTAI
VIHX×0.1
VILX
tR tF
3) With sine waves input to XTAI and VCOI pins via capacitor
(Topr= 20 to +75 °C, VDD=AVDD=5.0 VÄ…5 %)
Item Symbol Min. Typ. Max. Unit
Input amplitude V1 2.0 VDD+0.3 Vp-p
 9
CXD2500BQ
(1) CLOK, DATA, XLAT, CNIN, SQCK, and EXCK pins
(VDD=AVDD=5.0 VÄ…5 %, VSS=AVSS=0 V, Topr= 20 to +75 °C
Item Symbol Min. Typ. Max. Unit
Clock frequency fCK 0.65 MHz
Clock pulse width tWCK 750
Setup time tSU 300
Hold time tH 300 ns
Delay time tD 300
Latch pulse width tWL 750
EXCK, CNIN, SQCK frequency fT 1 MHz
EXCK, CNIN, SQCK pulse width tWT 300 ns
1/fCK
tWCK tWCK
CLOK
DATA
XLAT
tSU tH
tD tWL
EXCK
CNIN
SQCK
tWT tWT
1/fT
SUBQ
SQCK
tSU tH
Description of Functions
ż1 CPU Interface and Commands
" CPU interface
This interface is used to set various modes using DATA, CLOK, and XLAT.
The interface timing chart is shown below.
750ns or more
CLOK
DATA D1 D2 D3 D0 D1 D2 D3
Data Address
750ns or more
XLAT
Registers 4 to E
Valid
300ns max
" The command addresses of the CXD2500B and the data capable of being set are shown in Table 1-1.
" When XRST is set to 0, the CXD2500B is reset, causing its internal registers to be initialized to the values
listed in Table 1-2.
 10
Commands
Register Address Data 1 Data 2 Data 3 Data 4
Command
name D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0
4 Auto sequence 0 1 0 0 AS3 AS2 AS1 AS0            
Blind (A, E), Overflow (C) 0.18 ms 0.09 ms 0.045 ms 0.022 ms
5 0 1 0 1            
Brake (B) 0.36 ms 0.18 ms 0.09 ms 0.045 ms
6 KICK (D) 0 1 1 0 11.6 ms 5.8 ms 2.9 ms 1.45 ms            
Auto sequencer track
7 0 1 1 1 32,768 16,384 8,192 4,096 2,048 1,024 512 256 128 64 32 16 8 4 2 1
jump (N) setting
D OUT
8 MODE specification 1 0 0 0 CDROM 0 WSEL            
Mute-F
D CLV DSPB A SEQ D PLL BiliGL BiliGL
9 Func specification 1 0 0 1 FLFC         
ON-OFF ON-OFF ON-OFF ON-OFF MAIN SUB
Vari Vari
A Audio CTRL 1 0 1 0 Mute ATT PCT1 PCT2          
UP Down
Traverse monitor
B 1 0 1 1 32,768 16,384 8,192 4,096 2,048 1,024 512 256 128 64 32 16 8 4 2 1
counter setting
Gain Gain Gain Gain
C Servo factor setting 1 1 0 0            
MDP1 MDP0 MDS1 MDS0
DCLV CLVS
D CLV CRTL 1 1 0 1 TB TP            
PWM MD Gain
E CLV mode 1 1 1 0 CM3 CM2 CM1 CM0            
Table 1-1
 11
CXD2500BQ
Reset Initialization
Register Address Data 1 Data 2 Data 3 Data 3
Command
name D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0
4 Auto sequence 0 1 0 0 0 0 0 0            
Blind (A, E), Overflow (C)
5 0 1 0 1 0 1 0 1            
Brake (B)
6 KICK (D) 0 1 1 0 0 1 1 1            
Auto sequencer
7 0 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
track jump setting
8 MODE specification 1 0 0 0 0 0 0 0            
9 Func specification 1 0 0 1 1 0 0 1 0 0 0         
A Audio CTRL 1 0 1 0 0 0 1 1 0 0          
Traverse monitor
B 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
counter setting
C Servo factor setting 1 1 0 0 0 1 1 0            
D CLV CRTL 1 1 0 1 0 0 0 0            
E CLV mode 1 1 1 0 0 0 0 0            
Table 1-2
 12
CXD2500BQ
CXD2500BQ
ż1 Meanings of Data Set at Command Addresses
$4X Command
Command AS3 AS2 AS1 AS0
CANCEL 0 0 0 0
FOCUS-ON 0 1 1 1
1 TRACK JUMP 1 0 0 RXF
10 TRACK JUMP 1 0 1 RXF
2N TRACK JUMP 1 1 0 RXF
M TRACK MOVE 1 1 1 RXF
RXF=0 FORWARD
RXF=1 REVERSE
" If a Focus-ON command ($47) is canceled during execution, $02 is issued and the auto sequence operation
is discontinued.
" If a Track Jump or Track Move command ($48 to $4F) is canceled during execution, the auto sequence
operation is discontinued.
$5X Command
Used to set timers for the auto sequencer.
Timers set: A, E, C, and B
Command D3 D2 D1 D0
Blind(A, E), Overflow(C) 0.18 ms 0.09 ms 0.045 ms 0.022 ms
Brake(B) 0.36 ms 0.18 ms 0.09 ms 0.045 ms
Example: D2=D0=1, D3=D1=0 (Initial Reset)
A=E=C=0.112 ms
B=0.225 ms
$6X Command
Used to set a timer for the auto sequencer.
Timer set: D
Command D3 D2 D1 D0
KICK (D) 11.6 ms 5.8 ms 2.9 ms 1.45 ms
Example: D3=0 D2=D1=D0=1 (Initial Reset)
D=10.15ms
$7X Command
Used to set the number of auto sequencer track jumps/moves.
Data3 Data 2 Data 3 Data 4
Command
D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0
Auto sequencer track
215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20
jump number setting
This command sets the value of  N for 2N track jump and M track move execution using the auto sequencer.
 13
CXD2500BQ
" The maximum number of tracks that can be counted is 65,535. However, in the case of 2N track jumps, it is
subject to mechanical restrictions due to the optical system.
" When the number of tracks to be jumped is smaller that 15, the signals input from CNIN are counted. When
it is 16 or larger, the signals input from the MIRR pin are counted. This count signal selection contributes
toward improving the accuracy of high-speed track jumping.
Command D3 D2 D1 AS0
D. OUT
MODE specification CDROM 0 WSEL
Mute-F
$8X Command
Command C2PO timing Processing
CDROM mode is entered. In this mode, average value
CDROM=1 1-3
interpolation and preceding value holding are not performed.
Audio mode is entered. In this mode, average value
CDROM=0 1-3
interpolation and preceding value holding are performed.
Command bit Processing
D. out Mute F=1 When Digital Out is ON (pin MD2=1), DA output is muted.
D. out Mute F=0 Da output muting is unaffected by the setting of Digital Out.
D/A Out D.out Mute with F=1
MD2=1 MD2=0
(D. out-ON) (D. out-OFF)
Mute-ON  "dB  "dB
Mute-OFF  "dB 0dB
Command bit Sync protection window width Application
WSEL=1 Ä…26 channel clock pulses" Anti-rolling is enhanced.
WSEL=0 Ä…6 channel clock pulses Sync window protection is enhanced.
"
In normal-speed playback, the channel clock frequency is 4.3218 MHz.
$9X Command
Data 1 Data 2
Command
D3 D2 D1 D0 D3 D2 D1
DCLV DSPB A. SEQ D. PLL BiliGL BiliGL FLFC
Func specification
ON-OFF ON-OFF ON-OFF ON-OFF MAIN Sub
 14
CXD2500BQ
Command bit CLV mode Contents
FSW=L, MON-H, MDS-Z, MDP=servo control signal, with carrier
In CLVS mode
frequency of 230 Hz at TB=0 and 460 Hz at TB=1
DCLV ON-OFF=0
FSW=Z, MON=H, MDS=speed control signal with carrier frequency of
In CLVP mode
7.35 kHz, MDP=phase control signal with carrier frequency of 1.84 kHz
MDS= PWM polarity signal. Carrier
DCLV when frequency=132 kHz
PWM, MD=1 MDS= PWM absolute value output (binary).
DCLV ON-OFF=1
In CLVS or Carrier frequency=132 kHz
(FSW and MON are
CLVP mode
unnecessary) MDS= Z
DCLV when
MDP= ternay PWM output.
PWM, MD=0
Carrier frequency=132 kHz
In the Digital CLV servo mode with DCLV ON-OFF set to 1, the sampling frequency of the internal digital filter
is switched at the same time as the switching between CLVP and CLVS.
Therefore, for CLVS, the cut-off frequency fC is 70 Hz when TB is set to 0, and 140Hz when TB is set to 1.
Command bit Processing
Normal-speed playback. ECC quadruple error correction is made. Vari-pitch
DSPB=0
control is enabled.
Double-speed playback. ECC double error correction is made. Vari-pitch control
DSPB=1
is disabled.
Set FLFC at 1 when in double-speed playback mode (exclude the low power consumption special playback
mode). However, FLFC can be set to 0 during PLL pull-in (lock). Set to 0 for all other modes.
SENS Output
Microcomputer serial register
ASEQ=0 ASEQ=1
values (Latching unnecessary)
$0X Z SEIN (FZC)
$1X Z SEIN (A, S)
$2X Z SEIN (T. Z. C)
$3X Z SEIN (SSTOP)
$4X Z XBUSY
$5X Z FOK
$6X Z SEIN (Z)
$AX GFS GFS
$BX COMP COMP
$CX COUT COUT
$EX OV64 OV64
$7X, 8X, 9X, DX, FX Z 0
 15
CXD2500BQ
Description of SENS signals
SENS output Meaning
Z SENS is at High-Z state.
SEIN SEIN signal, which was input to the CXD2500B, is output from SSP.
XBUSY  L when auto sequencer is in operation;  H when terminated.
Output of the signal (normally FOK input from RF) input to the FOK pin.  H when
FOK
Focus OK is received.
GFS  H when regenerated Frame Sync is obtained at the correct time.
Used in counting the number of tracks set in register B.  H when the count is
COMP latched to register B twice in succession. It is reset to  L level when the count of
CNIN inputs equals the originally set number for register B.
Used in counting the number of tracks set in register B.  H when the count is
COUT latched to register B, then to register C. It is toggled every time the count of CNIN
inputs reaches the value set in register B.
 L when after passing through the sync detection filter, the EFM signal become
OV64
longer than the 64 channel clocks.
Command bit Meaning
DPLL=0 RFPLL enters analog mode. PDO, VCOI, and VCOO are used.
DPLL=1 RFPLL enters digital mode. PDO becomes Z.
BiliGL BiliGL
Command bit
MAIN=0 MAIN=1
BiliGL SUB=0 STEREO MAIN
BiliGL SUB=1 SUB Mute
Definition of Bilingual MAIN, SUB, and STEREO
MAIN; The input L-ch signal is output to both L-ch and R-ch.
Sub: The input R-ch signal is output to both L-ch and R-ch.
STEREO: The input L-ch and R-ch signals are output to both L-ch and R-ch respectively.
 16
CXD2500BQ
$AX Command
Data 1 Data 2
Command
D3 D2 D1 D0 D3 D2
Vari Vari
Audio CTRL Mute ATT PCT1 PCT2
UP DWN
Vari UP
Vari DWN
XTal 0% VCO 0% +0.1% +0.2% +0.3% +0.2% +0.1% +0% -0.1% -0.2% XTal 0%
Pitch
Command bit Meaning Command bit Meaning
Mute=0 Muting is off unless condition to make muting occurs. ATT=0 Attenuation is off.
Mute=1 Muting is on. Peak register reset. ATT=1  12dB
Condition for Muting
(1) Mute=1 in register A
(2) Pin Mute=1
(3) D.OUT Mute F=1 in register 8 with D.Out ON (MD2=1)
(4) Elapse of over 35 msec after GFS turns  Low
(5) BiliGL MAIN=Sub=1 in register 9
(6) PCT1=1 and PCT2=2 in register A
In the case of (1) to (4), zero-cross muting not exceeding 1 msec is performed.
Command bit
Meaning PCM Gain ECC correction capacity
PCT1 PCT2
00 Normal mode × 0 dB C1: Double, C2: Quadruple
01 Level meter mode × 0 dB C1: Double, C2: Quadruple
10 Peak meter mode Mute C1: Double, C2: Double
11 Normal mode × 0 dB C1: Double, C2: Double
Level Meter Mode (See Timing Chart 1-4.)
" This mode makes the digital level meter function available.
" Inputting 96-bit clock pulses to SQCK will enable 96 data to be output to SQSO. Of the output data, the first
80 bits comprise Sub-Q data, which transmit the description for the data format to the Sub Code interface.
The last 16 bits are ordered LSB-first, of which the first 15 bits constitute PCM data (absolute value). The
final 1 bit is  High if the prior PCM data was generated at the left channel;  Low if generated at the right
channel.
" The PCM data is reset once it is read, and the L/R flag is reversed. While this state is kept until the next
read operation is started, testing for the maximum value is conducted.
 17
CXD2500BQ
Peak Meter Mode (See Timing Chart 1-5.)
" In this mode, the maximum value of PCM data is detected whether the channel involved is L-ch or R-ch.
To read the detected maximum value, it is necessary to input 96 clock pulses to SQCK.
" When 96 clock pulses have been input to SQCK, 96 bits of data is output to SQSO. At the same time, the
data is re-set in an internal register of the LSI.
That is, the PCM peak detection register is not reset when it is read.
" To reset the PCM peak register, set both PCT1 and PCT2 to 0. Or, Set $AX mute.
" In this mode, the absolute time of Subcode Q is controlled automatical.
" Namely, every time a peak value is detected, the absolute time when the CRC was passed is stored. The
program time operation is performed in the normal way.
" The last bit (L/R flag) of the 96-bit data stays 0.
" In this mode, the preceding value holding and average value interpolation data are fixed to level ( ").
$CS Command
Command D3 D2 D1 D0 Explanation
Gain Gain Gain Gain
Servo factor setting Only DCLV=1 is effective.
MDP1 MDP0 MDS1 MDS0
Gain DCLV=1 and DCLV=0 are both
CLV CTRL ($DX)
CLVS effective.
This command is used to externally set the spindle servo gain when DCLV=1.
" Gain setting for CLVS mode: GCLVS
Gain Gain Gain GCLVS
MDS1 MDS0 CLVS
Note: When DCLV=0, the CLVS gain is
0 0 0  12dB
determined as follows:
0 0 1  6dB
If Gain CLVS=0, then GCLVS= 12 dB.
0 1 0  6dB
If Gain CLVS=1, then GCLVS=0 dB
011 0dB
100 0dB
1 0 1 +6dB
" Gain setting for CLVP mode: GMDP, GMDS
Gain Gain GMDP Gain Gain GMDS
MDP1 MDP0 MDS1 MDS0
0 0  6 dB 0 0  6dB
0 1 0 dB 0 1 0dB
1 0 + 6dB 1 0 +6dB
 18
CXD2500BQ
$DC Command
Command D3 D2 D1 D0
TP CLVS
DCLV
CLV CTRL TB
PWM MD Gain
See  $CX Command.
Command bit Description (See Timing Chart 1-6.)
DCLV PWM MD=1 Specification of PWM mode for digital CLV. Both MDS and MDP are used.
DCLV PWM MD=0 Specification of PWM mode for digital CLV. Ternary MDP values are output.
Command bit Description
TB=0 In CLVS or CLVH mode, bottom value is held at periods of RFCK/32.
TB=1 In CLVS or CLVH mode, bottom value is held at periods of RFCK/16.
TP=0 In CLVS mode, peak value is held at periods of RFCK/4.
TP=1 In CLVS mode, peak value is held at periods of RFCK/2.
In CLVH mode, peak holding is made at 34 kHz.
$EX Command
Command D3 D2 D1 D0
CLV mode CM3 CM2 CM1 CM0
CM3 CM2 CM1 CM0 Mode Explanation
0 0 0 0 STOP See Timing Chart 1-7.
1 0 0 0 KICK See Timing Chart 1-8.
1 0 1 0 BRAKE See Timing Chart 1-9.
1 1 1 0 CLVS
1 1 0 0 CLVH
1 1 1 1 CLVP
0 1 1 0 CLVA
STOP: Spindle motor stop mode
KICK: Spindle motor forward run mode
BRAKE: Spindle motor reverse run mode
CLVS: Rough servo mode for use for pulling disc run into RF-PLL capture range when the RF-PLL circuit
lock has been disengaged
CLVP: PLL servo mode
CLVA: Automatic switching mode for CLVS and CLVS. This mode is used during normal play status.
 19
Timing Chart 1-3
LRCK
48bit Slot
WDCK
CDROM=0
If C2 pointer=1,
C2PO Rch 16bit C2 Pointer Lch 16bit C2 Pointer
data is NG
CDROM=1
C2PO C2 Pointer for upper 8bit C2 Pointer for Lower 8bit C2 Pointer for upper 8bit C2 Pointer for Lower 8bit
Rch C2 pointer Lch C2 pointer
 20
CXD2500BQ
Timing Chart 1-4
750ns to 120µs
1 2 3 80 81 96
SQCK
SQSO CRCF D0 D1 D2 D3 D4 D5 D6 D13 D14 L/R
15-bit peak-data
Sub-Q Data
See "Sub Code interface" Absolute value display, LSB first
Peak data
L/R flag
1 23
1 23
WFCK
96 clock pulses 96 clock pulses
SQCK
SQSO L/R CRCF R/L CRCF
16 bit
96 bit data Peak data of this section
Hold section
Level Meter Timing
 21
CXD2500BQ
Timing Chart 1-5
123 123
WFCK
96 clock pulses 96 clock pulses
SQCK
CRCF
CRCF CRCF
Measurement
Measurement Measurement
Peak Meter Timing
 22
CXD2500BQ
CXD2500BQ
Timing Chart 1-6
DCLV PWM MD=0
MDS
Z
n·236 (nsec) n=0 to 31
Acceleration
MDP
Z
132KHz
7.6µSec
Deceleration
DCLV PWM MD=1
MDS
Acceleration Deceleration
MDP
n·236 (nsec) n=0~31
7.6µSec
Output Waveforms with DCLV=1
Timing Chart 1-7
STOP
DCLV=0
MDS
Z
MDP
L
FSW
L
MON
L
DCLV=1 DCLV PWM MD=0
STOP
MDS
Z
MDP
Z
DCLV=1 DCLV PWM MD=1
STOP
MDS
MDP
L
FSW and MON are the same as for DCLV=0
 23
CXD2500BQ
Timing Chart 1-8
KICK
DCLV=0
Z
MDS
MDP
H
L
FSW
MON
H
DCLV=1 DCLV PWM MD=0
KICK
Z
MDS
MDP H
Z
7.6µs
FSW and MON are the same as for DCLV=0
DCLV=1 DCLV PWM MD=1
KICK
MDS
H
MDP
H
L
FSW and MON are the same as for DCLV=0
 24
CXD2500BQ
Timing Chart 1-9
BRAKE
DCLV=0
MDS
Z
MDP
L
FSW
L
MON
H
DCLV=1 DCLV PWM MD=0
BRAKE
MDS
Z
MDP
L Z
FSW and MON are the same as for DCLV=0
DCLV=1 DCLV PWM MD=1
MDS
MDP
FSW and MON are the same as for DCLV=0
 25
CXD2500BQ
ż2 Subcode Interface
In this section, the subcode interface will be explained.
The contents of the subcode interface can be externally read in two ways. The subcodes P through W totaling
8 bits can be read from SBSO by inputting EXCK to the CXD2500B.
Sub-Q can be read after conducting a CRC check on the 80bits of information in the subcode frame. First,
check SCOR and CRCF, then input 80 clock pulses to SQCK and read the data.
ż2-1 P-W Subcode Read
These subcodes can be read by entering EXCK immediately after the fall of WFCK. (See Timing Chart 2-1.)
ż2-2 80-bit Sub-Q Read
Figure 2-2 shows a block diagram of the peripheral part of the 80-bit Sub-Q register.
" The Sub Q regenerated on a bit-per-frame basis is input to the 80-bit serial/parallel register and the CRC
circuit.
" When the results of CRC of the 96-bit Sub-Q are OK, CRCF is set to 1 and the 96-bit data is output to
SQSO.
Furthermore, it is loaded into the 80-bit, parallel/serial register.
If SQSO is  H after the output of SCOR, it can be taken that CPU has been loaded a new set of CRCOK
data.
" When 80-bit data is loaded into CXD2500B, MSB and LSB are reversed within each byte of the data.
Therefore, the bits are ordered LSB-first within each byte, even though the byte arrangement is kept
unchanged.
" When 80 bits of data are confirmed to have been loaded, SQCK is input to read the data. Subsequently in
the CXD2500B, the input of SQCK is detected and the retriggerable monostable multivibrator is reset during
Low.
" The time constant of the retriggerable monostable multivibrator ranges from 270 to 400 µs. If the time of
High for SQCK is less than this time constant, the monostable multivibrator will keep resetting, preventing the
contents of the P/S register from being loaded into the P/S register.
" While the monostable multivibrator is resetting, data loading into the peak detection parallel/serial register
and 80-bit parallel/serial register is forbidden.
Therefore, while data read operation is carried out at clock periods shorter than the time constant of the
monostable multivibrator, the contents of these registers are retained without being rewritten by CRCOK, etc.
" The CXD2500B permits the peak detection register to be connected to the shift-in of the 80-bit P/S register.
For Ring Control 1, the input and output are short-circuited during peak meter and level meter mode.
For Ring Control 2, the input and output are short-circuited during peak meter mode only.
The Ring Controls are arranged in this way in order for the registers to be reset each time their contents are
read in the level meter mode, while preventing destructive read in the peak meter mode.
To enable this control, 96 clock pulses must be input to the peak meter mode.
" As afore mentioned, in the peak meter mode, the absolute time following the generation of a peak value is
stored.
These operations are shown in Time chart 2-3.
Note: To perform the above operations, the duration of the clock pulse input to SQCK must be between 750ns
and 120 µs for both  High and  Low .
 26
CXD2500BQ
Timing Chart 2-1
Internal
PLL c lock
4.3218Ä…"MHz
WFCK
SCOR
EXCK
750ns max
SBSO S0·S1 Q R
WFCK
SCOR
EXCK
SBSO S0·S1 Q R S T U V W S0·S1 P1 Q R S T U V W P1 P2 P3
Same Same
Subcode P. Q. R. S. T. U. V. W Read Timing
 27
Block Diagram 2-2
ADDRS CTRL
(ASEC)
(AFRAM) (AMIN)
SIN
SUB-Q
80 bit S/P Register
C D G
A B E F H
8 8 8 8 8 8 8 8 8
Order
Inversion
SO
H G F E D C B A
80 bit P/S Register
SI
Monostable
ABS time load control
CRCC SHIFT
SHIFT SQCK
multivibrator
for peak value
LOAD CONTROLE
LD
SO SI
CRCF
Ring control 1 16 bit P/S register Ring control 2
SQSO
Mix
16
Peak detection
LD
LD
LD
LD
LD
LD
LD
LD
SUBQ
 28
CXD2500BQ
Timing Chart 2-3
1 2 3 91 92 93 94 95 96 97 98
1 2 3
WFCK
Order
SCOR
Inversion
Determined by mode
SQSO CRCF 1 CRCF 1 CRCF 2
80 or 96 Clock
SQCK
Register load forbidder
Monostable
multivibrator
(Internal)
When SQCK=High, 270 to 400µsec
750ns to 120µs
SQCK
SQSO
CRCF ADR0 ADR1 ADR2 ADR3 CTL0 CTL1 CTL2 CTL3
300ns max
 29
CXD2500BQ
CXD2500BQ
ż3 Other Functions
ż3-1 Channel Clock Regeneration Using Digital PLL Circuit
" Demodulation of regenerated EFM signals using an optical system requires the use of channel clock pulses.
The EFM signal to be demodulated has been modulated into an integer multiple of the channel clock period
T, ranging from 3T to 11T.
To read the information conveyed by the EFM signal, it is essential to correctly recognize the integral value;
hence, the need to use channel clock pulses.
In an actual CD player, the pulse width of the EFM signal will vary, affected by fluctuations of the disc
rotation. For this reason, it is necessary to use a PLL in regenerating channel clock pulses.
Figure 3-1 shows a block diagram of the 3-stage PLL contained in the CXD2500B.
" The 1st-stage PLL is used for vari-pitch regeneration. To use this PLL, LPF and VCO are necessary as
external parts.
The minimum pitch variable possible is 0.1 %. The output of this 1st-stage PLL is used as the standard for
all the clock pulses used in the LSI.
When vari-pitch control is not in uses, connect the output pin of XTAO to VCKI.
" The 2nd-stage PLL generates high frequency clock pulses necessary for the 3rd-stage digital PLL.
" The 3rd-stage comprises a digital PLL used to regenerate the actual channel clock pulses. It realizes a
capture range of Ä…150 kHz (normal conditions) or more.
" The digital PLL features a secondary loop. It is controlled through the primary loop (phase) secondary loop
(frequency).
When FLFC=1, the secondary loop can be turned off.
" When high frequency components such as 3T, 4T, are deviated, turning off the secondary loop will provide
better play ability.
" However, the capture range will be 50 kHz.
 30
CXD2500BQ
Block Diagram 3-1
OSC
16,9344MHz
X'Tal
1/1000
1/4
(384Fs)
LPF
VPCO
XTSL
1/4 1/1000+n
VCO
19. 78 to 13.26MHz
VCKI
2/1 MUX
Up down counter
Vari-pitch
n=-217 to 168
Microcomputer control Vari-pitch
I/M
PCO
I/N
FILI
FILO
CLTV
VCO
Digital PLL
RFPLL
D2500B
 31
Phase comparator
Phase comparator
CXD2500BQ
ż3-2 Frame Sync Protection
" During CD player operation at normal speed, Frame Sync is recorded approximately once every 136 µs (at
7.35 kHz).
This signal can be used to identify the data within each frame. When Frame Sync cannot be recognized, the
data also cannot be identified; as a result, it is treated as an error. Therefore, correct Frame Sync
recognition is very important to ensure high play ability for the CD player.
" The CXD2500B employs window protection, front protection and rear protection to realize a powerful Frame
Sync protection. The CXD2500B offers two window widths, one for use when the player is subjected to
rotational disturbance and the other for use without such disturbance (WSEL=0/1).
The front protection counter is fixed at 13 and the rear protection counter at 3. Therefore, during normal play
back, when the frame sync cannot be detected due to damages on the disc. If the number to frames with
undetected Frame Sync exceeds 13, the window is released and the Frame Sync signal are re-synchronized.
If no Frame Sync is correctly detected in 3 successive frames immediately after Frame Sync re-
synchronization performed following a window release, the window is released at once.
ż3-3 Error Correction
" On CDs, each data unit (8 bits) is formatted so that it is contained in two correction codes, C1 and C2. C1
consists of 28 bytes of information and 4-byte parity, whereas C2 is made up of 24 bytes of information and
4-byte parity. Both C1 and C2 comprise a read Solomon code with a minimum distance of 5.
" C1 realizes double corrections and C2 realizes quadruple corrections, both by the refined superstrategy
method.
" To prevent erroneous C2 corrections, C1 pointer based on the conditions of C1 error, EFM signal play back,
and player operation during C1 operation is attached to the corrected data.
" The status of error correction can be monitored from outside the LSI. It is indicated as shown in Table 3-2.
" When C2 pointer is High, this signifies uncorrectable data error. The data are either previous data held
subsitute the error, or an average value interpolation.
MNT3 MNT2 MNT1 MNT0 Description
0000 C1: No error detected. C1 pointer reset.
0001 C1: 1 error corrected. C1 pointer set.
0010 
0011 
0100 C1: No error detected. C1 pointer set.
0101 C1: 1 error corrected. C1 pointer set.
0110 C1: 2 errors corrected. C1 pointer set.
0111 C1: Uncorrectable error. C1 pointer set.
1000 C2: No error detected. C2 pointer reset.
1001 C2: 1 error corrected. C2 pointer reset.
1010 C2: 2 errors corrected. C2 pointer reset.
1011 C2: 3 errors corrected. C2 pointer reset.
1100 C2: 4 errors corrected. C2 pointer reset.
1101 
1110 C2: Uncorrectable error. C1 pointer copied.
1111 C2: Uncorrectable error. C2 pointer set.
Table 3-2 Indication of error correction status
 32
CXD2500BQ
Timing Chart 3-3
Normal - speed PB
400 to 500nsec
RFCK
t=Dependent on error
condition
MNT3
C2 correction
C1 correction
MNT2
MNT1
MNT0
Strobe Strobe
C4M
MNT0 to 3
Valid
Valid
Invalid
ż3-4 DA Interface
" The CXD2500B has two modes of DA interface.
a) 48-bit slot interface
This is an MSB-first interface made up of LRCK signals with 48-bit clock cycles per LRCK cycle. While
the LRCK signal is High, the data going through this interface is of the left channel.
b) 64-bit slot interface
This is an LSB-first interface made up of LRCK signals with 64-bit clock cycles per LRCK cycle. While
the LRCK signal is Low, the data going through this interface is of the left channel.
 33
Timing Chart 3-4
48 bit slot Normal-Speed Playback PSSL=L
LRCK
(44.1K)
1 2 3 4 5 6 7 8 9 10 11 12 24
DA15
(2.12M)
WDCK
DA16 R0 L ch MSB (15) L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 RMSB
48 bit slot Double-Speed Playback
LRCK
(88.2K)
1 2 24
DA15
(4.23M)
WDCK
DA16
R0 L ch MSB (15) L0 R ch MSB
 34
CXD2500BQ
Timing Chart 3-5
64 Bit slot Normal Speed PB PSSL=L
DA 12
(44.4K)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 20 30 31 32
DA 13
(2.82M)
R ch LSB (0) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 R15 L ch LSB (0)
DA 14
64 Bit slot Double Speed PB
DA 12
(88.2K)
1 2 3 4 5 10 15 20 25 30 31 32
DA 13
(5.64M)
DA 14
R ch LSB (0) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 L ch LSB
L15
 35
CXD2500BQ
CXD2500BQ
ż3-5 Digital Out
There are three digital-out formats: type 1 for use at broadcasting stations, type 2, form 1 for use in general
civil applications, and type 2, form 2 for use in software production. The CXD2500B supports type 2, form 1.
The clock accuracy for the channel status is automatically set at Level II when the X'tal clock is used, or
Level III when vari-pitch control is made.
CRC checks are conducted on the Sub-Q data on the first 4 bits (bits 0-3). The data is input only after two
checks are passed in succession.
The X'tal clock is set to 34 MHz, and variable pitch is reset. When D out is output at DSPB=1, set MD2 to 0
and turn off D out 34.
Digital Out C bit
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
From sub-Q
0 0 0 0 0 1 0 0 0 0 0 0 0
ID0 ID1 COPYEmph
16 0 0 0 0 0 0 0 0 0 0 0 0 0 0/1 0 0
32
48
0
176
Bits 0-3: Sub-Q control bits required to pass the CRC twice in succession.
bit 29: Varipitch: 1 X'tal: 0
Table 3-6 Digital Out C bits
ż3-6 Servo Auto Sequencer
The servo auto sequencer controls a series of operation including auto-focusing and track jumping. When an
auto sequence command is received from CPU, the servo auto sequencer automatically executes auto-
focusing, 1-track jumping, 2N track jumping and M track moving.
During auto sequence execution (X Busy=Low), as SSP (servo signal processing LSI) is used exclusively,
commands from CPU are not transferred to SSP. Instead, the commands can be sent to CXD2500B.
To make this servo auto sequencer usable, connect a CPU, RF and SSP to the CXD2500B as shown in
Figure 3-7 and set A.SEQ ON-OFF of Register 9 to ON.
When the CLOK changes from Low to High while XBUSY is at Low, from that point on to a maximum of 100
µsec, X BUSY does not become High.
Due to the monostable multivibrator which is reset when CLOK is Low (XBUSY=Low), transfer of erroneous
data to SSP is prevented when XBUSY changes from Low to High.
 36
CXD2500BQ
(a) Auto Focus ($47)
In auto focus operation,  focus search up is performed, FOK and FZC are checked, and the focus servo
is turned on. When $47 is received from CPU, the focus servo is turned on through the steps shown in
Figure 3-8. Since this auto focus sequence begins with  focus search up, it requires the pickup to be
put down (focus search down) beforehand.
Blind E of Register 5 is used to eliminate chattering from FZC. The focus servo is turned on at the
trailing edge of FZC after staying High continuously for a longer period than E.
System Configuration for Auto Sequencer Operation (Example)
RF
MIRR
MIRR DATA
FOK
FOK CLOK
Micro-computer
XLAT
SENS
CXD2500B
C.out CNIN
SENS SEIN
DATA DATO
SSP
CLK CLKO
XLT XLTO
Figure 3-7
 37
CXD2500BQ
Auto focus
Focus search up
Checking whether FZC has stayed High
longer than time E set in Register 5.
FOK=H
NO
YES
FZC=H
NO
YES
FZC=L
NO
YES
Focus servo ON
END
Figure 3-8 (a) Flow chart of auto focus operation
$47 latch
XLAT
FOK
SEIN(FZC)
BUSY
Blind E
Command to SSP $03 $08
Figure 3-8 (b) Timing chart for auto focus operation
 38
CXD2500BQ
(b) Track Jump
Track jump operation includes 1, 10 and 2N track jumps. Do not perform this track jump unless the focus,
tracking and sled servos are on. Such steps as tracking gain up and braking are not included in this track
jump. Therefore, the commands for tracking gain up and brake ON ($17) must be issued in advance.
" 1-track jump
When a $48 is received from CPU (or a $49 from REV), the servo auto sequencer executes a FWD
(REV) 1-track jump as shown Figure 3-9. The values of blind A and brake B must be set in Register 5.
" 10-track jump
When a $4H is received from CPU (or a $4B from REV), the servo auto sequencer executes a FWD
(REV) 10-track jump as shown in Figure 3-10. The principal difference between the 1-track and 10-track
jumps is whether the sled is kicked or not. In the 10-track jump, the actuator after being kicked is braked
when CNIN has been counted 5 tracks. When the actuator has adequately slowed down as a result of
braking, the tracking and sled servos are turned on (this actuator slow-down is detected by checking
whether the CNIN period has exceeded overflow C specified in Register 5).
" 2N track jump
When a $4C is received from CPU (or a $4D from REV), the servo auto sequencer executes a FWD
(REV) 2N track jump. The number of tracks to be jumped is determined by N, set Register 7 beforehand.
The maximum permissible number is 216. In actual use, however, it is subject to limitation imposed by the
actuator.
When N is smaller than 16, the jumps are counted by means of counting CNIN signals. If N is 16 and
above, MIRR signals are counted instead of CNIN signals.
The 2N track jump sequence is basically the same as the 10-track jump sequence. The only difference
between them is that, in the 2N track jump sequence, the sled is kept moving for time D specified in
Register 6 after the tracking servo is turned on.
" M track move
When a $4E is received from CPU (or a $4F from REV), the servo auto sequencer executes a FWD
(REV) M-track move as shown in Figure 3-12. The maximum value that can be set from M is 216. The
track moves are counted in the same way as for 2N track jumps. That is, when M is smaller than 16, the
moves are counted by means of counting CNIN signals. If M is 16 and above, MIRR signals are counted
instead of the CNIN signals. In this M track move, only the sled is moved. This method is suitable for a
large track move ranging from several thousand to several tens of thousand tracks.
 39
CXD2500BQ
1 Track
Track Kick
(REV kick is made for REV jump.)
Sled servo
WAIT
(Blind A)
CNIN=
NO
YES
Track REV
(FWD kick is made for REV jump.)
Kick
WAIT
(Brake B)
Track sled
Servo ON
END
Figure 3-9 (a) Flow chart of 1-track jump
$48 (REV=$49) latch
XLAT
CNIN
BUSY
Blind A
Brake B
Commands to SSP $28 ($2C) $2C ($28) $25
Figure 3-9 (b) Timing chart for 1-track jump
 40
CXD2500BQ
10 Track
Track, Sled
FWD Kick
WAIT
(Blind A)
(5 CNINs are counted.)
CNIN=
5?
NO
YES
Track, REV
Checking whether the CNIN period has
FWD Kick
exceeded the value of overflow C.
C=Overflow?
NO
YES
Track, Sled
Servo ON
END
Figure 3-10 (a) Flow chart of 10-track jump
$4A (REV=$4B) latch
XLAT
CNIN
BUSY
Blind A CNIN 5count Overflow C
Commands to SSP $2A ($2F) $2E ($2B) $25
Figure 3-10 (b) Timing chart for 10-track jump
 41
CXD2500BQ
2N Track
Track, Sled
FWD Kick
WAIT
(Blind A)
For the first 16 times CNIN is counted.
After that MIRR is counted.
CNIN (MIRR) =N
NO
YES
Track, REV
Kick
C=Overflow
NO
YES
Track Servo
ON
WAIT
(Klick D)
Sled Servo
ON
END
Figure 3-11 (a) Flow chart of 2N track jump
$4C (REV=$4D) latch
XLAT
CNIN
(MIRR)
BUSY
Blind A CNIN (MIRR) Kick D
Overflow
N count
Commands to SSP $2A ($2F) $2E ($2B) $26 ($27) $25
Figure 3-11 (b) Timing chart for 2N track jump
 42
CXD2500BQ
M Track move
Track Servo OFF
Sled FWD Kick
WAIT
(Blind A)
CNIN is counted for M<16, MIRR
is counted for Me"16.
CNIN (MIRR) =M
NO
YES
Track, Sled
Servo ON
END
Figure 3-12 (a) Flow chart of M track move
$4E (REV=$4F) latch
XLAT
CNIN
(MIRR)
BUSY
CNIN (MIRR) M count
Blind A
Commands to SSP $22 ($23) $25
Figure 3-12 (b) Timing chart for M track move
 43
CXD2500BQ
ż3-7 Digital CLV
The digital CLV is a digital spindle servo, of which its block diagram is shown in Figure 3-14. It is capable of
outputting MDS or MDP error signals by the PWM method after raising the sampling frequency up to 130 kHz
based on the normal speed in the CLVS, CLVP and other modes. It also permits gain setting.
Digital CLV
CLVS U/D MDS Error MDP Error
Gain
0,  6dB Measure Measure
Over Sampling
CLV P/S
2/1 MUX
Filter-1
Gs(Gain) GP(Gain)
CLV P
1/2
+
Mux
CLV S
CLV  P/S
Over Sampling
Filter-2
Noise Shape
KICK, BRAKE STOP
Modulation
MDP
Mode Select
MDS
DCLVMD
Figure 3-14 Block diagram
 44
CXD2500BQ
ż3-8 Asymmetry correction
Block diagram and circuit example are shown on Fig. 3-15.
D2500B
28
ASYE
ASYO
R1
27
RF
24
R1
R1
R2
ASYI
26
R1
25
BIAS
R1 2
=
R2 5
Figure 3-15 Asymmetry correction application circuit example
 45
CXD2500BQ
Application Circuit
TD
FD
SLD
SPD
GND
GND
GND
C12
SL+
FDFCT
SLO
FE
SL- FZC
ATSC
FSET
C13 FE
ISET TDFCT
TE
SSTOP TE
RF
C14
CXA1372Q
TZC
AVee
LDON
DIRC DVee
VCC
LOCK
RFO
V0
CLK
RFI
VCC
XLT
CP
DATA
CB
GND
GND GND GND
GND
AVDD
1M
BIAS
MIRR
GND
ASTI CLKO
VCC
ASTO XLTO
ASYE DATO
MUTE
NC
CNIN
SCOR
GND GND
PSSL
SEIN
SQCK
WDCK (48) CLOK
SUBQ
LRCK (48) VDD
GFS
CXD2500BQ
VDD
XLAT
CLK
DATA (64) DATA
XLT
BCLK (64) XRST
DATA
DATA (64) SENS
XRST
BCLK (64)
MUTE SENS
LRCK (64) FOK
SQCK
GTOP
SQSO LDON
EXCK
XUGF
Vee
GND
VCC
C2PO
GND GND
MUTE
BCLK
DATA
WDCK
GND GND
LRCK
DEMP
GND
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party and other right due to same.
 46
SLED-D
SPIND-D
FOCUS-D
SSTOP
GND
GND
GND
GND
GND
TRACK-D
GND
R2
R5
R1
R9
R7
C26
C9
C28
R6
GND
C23
C10
GND
R10
12
11
10
GND
9
8
7
6
5
4
3
2
FGD
1
VC
GND
FLB
FS3
TG2
GND
TA-
FE-
SRCH
TAO
FEO
AV
CC
TGU
C27
R4
R3
GND
13 14
15 16 17 18 19 20 21
22 23 24
48 47 46 45
44 43 42 41 40
39 38 37
C35
R14
R13
RV1
R11
GND
C11
RV2
R12
GND
FE
TE
RF
C15
C16
GND GND
COUT
26
DGND
SENS
27
XRST
DFCT
MIRR
DV
CC
C17
FOK
ASY
CC1
CC2
EFM
25
28
29
30
31
32
33
34
35
36
DFCT
FOK
MIRR
24
RF
23
22
21
20
PCO
19
18
17
16
VPCO
15
14
13
12
11
10
9
8
7
NC
6
5
4
3
2
1
FILO
FSW
NC
NC
NC
MOS
MOP
TEST1
LOCK
MON
VCKI
AV
SS
200p
VCOI
FOK
AV
DD
FILI
V
SS
VCOO
CLTV
PDO
25 26
27 28 29 30 31 32 33
34 35 36 37 38 39 40
80 79 78 77
76 75 74 73
72 71 70
69 68 67 66
65
GND
GND
WFCK
EMPH
SCOR
DOUT
C16M
SBSO
PLCK
APTR
RFCK
C2PO
RADF
MNT3
MNT2
MNT1
MNT0
XTAO
APTL
XTSL
FSTT
XTAI
MO2
C4M
GFS
V
SS
GND
50
52
53
54
55
56
57
58
59
60
61
62
63
64
41
42
43
44
45
46
47
48
49
51
DOUT
WFCK
RFCK
RAOV
PLCK
GFS
GND
MNT3
MNT2
MNT1
MNT0
UGFS
STTP
GND
CXD2500BQ
Package Outline Unit : mm
CXD2500BQ
80PIN QFP (PLASTIC)
23.9 Ä… 0.4
+ 0.1
+ 0.4 0.15  0.05
20.0  0.1
0.15
64
41
65
40
A
+ 0.2
80 25
0.1  0.05
1 24
+ 0.15 + 0.35
0.8 0.35  0.1 2.75  0.15
0.12 M
0° to 10°
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL EPOXY RESIN
SONY CODE QFP-80P-L01 LEAD TREATMENT SOLDER PLATING
EIAJ CODE "QFP080-P-1420-A LEAD MATERIAL COPPER / 42 ALLOY
JEDEC CODE PACKAGE WEIGHT 1.6g
CXD2500BQ
80PIN QFP (PLASTIC)
24.0 Ä… 0.3
+ 0.4
20.0  0.1
64 41
65 40
+ 0.2
80 25
0.1  0.05
1 24
+ 0.15
0° to 10°
0.8 0.35  0.1 2.7 Ä… 0.1
Ä… 0.12 M
0.15
3.1 MAX
22.6
PACKAGE STRUCTURE
PACKAGE MATERIAL EPOXY RESIN
SONY CODE QFP-80P-L121 LEAD TREATMENT SOLDER PLATING
"QFP080-P-1420-AX LEAD MATERIAL 42 ALLOY
EIAJ CODE
JEDEC CODE PACKAGE WEIGHT 1.6g
 47
+ 0.4
16.3
17.9 Ä… 0.4
14.0  0.1
0.8 Ä… 0.2
+ 0.4
16.6
18.0 Ä… 0.3
14.0  0.1
+ 0.1
0.15  0.05
0.1
0.7 Ä…
CXD2500BQ
CXD2500BQ
QFP 80PIN (PLASTIC)
23.9 Ä… 0.2
"20.0 Ä… 0.2
64 41
65
40
A
25
80
24
1
0.35 Ä… 0.1 4  0.8
0.15 M
1.45
0.15
0° to 10°
DETAIL A
NOTE: Dimension  " does not include mold protrusion.
PACKAGE STRUCTURE
PACKAGE MATERIAL EPOXY RESIN
SONY CODE QFP-80P-L051 LEAD TREATMENT SOLDER PLATING
EIAJ CODE "QFP080-P-1420-AH LEAD MATERIAL 42 ALLOY
JEDEC CODE 1.6g
PACKAGE WEIGHT
 48
0.8
17.9 Ä… 0.2
"
14.0 Ä… 0.2
4  1.0
0.8 Ä… 0.15
1.95 Ä… 0.15
+ 0.20
2.7  0.16
0.24 Ä… 0.15
2.94 Ä… 0.15
0.15 Ä…
0.05
15°
15°
C1.2
15°
15°


Wyszukiwarka

Podobne podstrony:
CXD2500DQ APLIK

więcej podobnych podstron