Podstawy techniki
mikroprocesorowej
ETEW006
Grupy rozkazów, dekodowanie
i wykonywanie rozkazów,
tryby adresowania
Andrzej Stępień
Katedra Metrologii Elektronicznej i Fotonicznej
Linia kodu programu
instrukcja
mnemonik instrukcji [operand1], [operand2], ..
[etykieta:] [; komentarz]
dyrektywa
etykieta - symboliczny adres,
instrukcja - rozkaz wykonywany przez procesor,
mnemonik - symboliczna nazwa instrukcji,
operand - argumenty instrukcji,
dyrektywa - polecenie dla asemblera,
komentarz - tekst pomijany przez asembler, od  ; do CR LF
Steve Furber: ARM System-on-Chip Architecture.
2nd Edition. Addison Wesley, 2001, ISBN-10: 0-201-67519-6
Figure 1.6
MU0
memory
Simple Processor
MEMrq RnW
" program counter (PC) register -
MU0
used to hold the address of the
IRce
current instruction
IR
" accumulator (ACC) - single
register, holds a data value while opcode
it is worked upon
PC
ACCoe
" arithmetic-logic unit (ALU) -
PCce
perform a number of operations Asel
on binary operands, such as add,
ALU
ALUfs
B A
subtract, increment, and so on
" instruction register (IR) - holds ACCce
the current instruction while it is
ACC[15]
executed
ACC
ACCz
" instruction decode and control
mux
Bsel
0 1
logic that employs the above
components to achieve the
desired results from each
instruction
1
mux
0
Instruction Opcode Effect
LDA S 0000 ACC := mem16[S]
MU0
STO S 0001 mem16[S] := ACC
Basic
ADD S 0010 ACC := ACC + mem16[S]
SUB S 0011 ACC := ACC  mem16[S]
Components
JMP S 0100 PC := S
JGE S 0101 if ACC e" 0 PC := S
opcode S (memory address)
JNE S 0110 if ACC `" 0 PC := S
4 bits 12 bits
STP 0111 stop
MU0 is a 16-bit machine with a 12-bit address space , so it can address up
to 8 Kbytes of memory arranged as 4,096 individually addressable 16-bit
locations.
Instructions are 16 bits long, with a 4-bit operation code (or opcode) and
a 12-bit address field (S). The simplest instruction set uses only eight of the
16 available opcodes.
An instruction such as 'ACC := ACC + mem16[S]' means 'add the contents
of the (16-bit wide) memory location whose address is S to the
accumulator'. Instructions are fetched from consecutive memory addresses,
starting from address zero, until an instruction which modifies the PC is
executed, whereupon fetching starts from the new address given in the 'jump'
instruction.
MU0 - Instruction set design
basic machine operation such as an instruction to add two numbers to
produce a result
most general form:
 instruction requires some bits to differentiate it from other instructions,
 some bits to specify the operand addresses,
 some bits to specify where the result should be placed (destination),
 and some bits to specify the address of the next instruction to be
executed
4/3/2/1/0 - address instructions format
4 / 3 - address instructions format
4-address instructions format:
ADD d, s1, s2, next_i ; d := s1 + s2
; format requires 4n + f bits per instruction
f bits n bits n bits n bits n bits
function op 1 addr op 2 addr dest addr next_i addr
3-address instruction format (reduce the number of bits required for
each instruction is to make the address of the next instruction implicit - if
we assume that the default next instruction can be found by adding the
size of the instruction to the PC:
ADD d, s1, s2 ; d := s1 + s2
; format requires 3n + f bits per instruction
f bits n bits n bits n bits
function op 1 addr op 2 addr dest addr
2 / 1 / 0 - address instructions format
2-address instructions format - saving in the number of bits required
to store an instruction can be achieved by making the destination
register the same as one of the source registers:
ADD d, s1 ; d := d + s1
n bits
f bits n bits
function op 1 addr dest addr
function op 1 addr dest addr
1-address instructions format - if the destination register is made
implicit it is often called the accumulator:
f bits n bits
ADD s1 ; acc := acc + s1
function op 1 addr
function op 1 addr
0-address instructions format - an architecture may make all operand
references implicit by using an evaluation stack:
ADD ; top_of_stack := top_of_stack + next_on_stack
f bits
function
function
UM10344. P89LPC9151/9161/9171 User manual.
NXP Semiconductors, 7 January 2010, Rev. 01, p.128-130
C51 Instruction Set (111 Instructions)
MCU control NOP
Load and Transfer MOV, MOVC, MOVX, XCH, XCHD
data
transfer
Stack operation PUSH, POP
Logical operations ANL, ORL, XRL, CLR, CPL
Bit Operation CLR, SETB, CPL, ANL, ORL, MOV
logic
Shift and Rotates RL, RLC, RR, RRC, SWAP
Arithmetic operations ADD, ADDC, SUBB, MUL, DIV, DA
arithme-
tic
Increment/Decrement INC, DEC
Interruption management RETI
control
Unconditional Jump or Call ACALL, LCALL, RET
transfer
Conditional Branch JZ, JNZ, JC, JNC, JB, JNB, JBC,
CJNE, DJNZ
ST7 FAMILY. PROGRAMMING MANUAL.
STMicroelectronics, November 2005, p.30
C51 Instruction Set (111 Instructions)
ST7 Instruction Set (63 Instructions)
MCU control NOP
Load and Transfer LD, CLR
data transfer
Stack operation PUSH, POP, RSP
Logical operations AND, OR, XOR, CPL, NEG
Shift and Rotates SLL, SRL, SRA, RLC, RRC, SWAP, SLA
Bit Operation BSET, BRES
logic
Tests TNZ, BCP
Code Condition Flag modification SIM, RIM, SCF, RCF
Arithmetic operations ADC, ADD, SUB, SBC, MUL
arithmetic
Increment/Decrement INC, DEC
Compare CP
Interruption management TRAP, WFI, HALT, IRET
Unconditional Jump or Call JRA, JRT, JRF, JP, CALL, CALLR, RET
Conditional Branch JRxx
control transfer
Conditional Bit Test and Branch BTJT, BTJF
MSP430x4xx Family. User s Guide.
Texas Instruments 2007, SLAU056G p.3-17
C51 Instruction Set (111 Instructions)
ST7 Instruction Set (63 Instructions)
MSP430 Core Instruction Set (27 Instructions)
Load and Transfer MOV
data transfer
Stack operation PUSH
Logical /Bit operations BIT, BIC, BIS, XOR
logic
Shift and Rotates RRC, RRA, SWPB
Arithmetic operations ADD, ADDC, SUB, SUBC,
DADD, SXT
arithmetic
Increment/Decrement INC, DEC
Compare and Tests CMP
Interruption management RETI
Unconditional Jump or Call JMP, CALL
Conditional Branch JEQ/JZ, JNE/JNZ,
control transfer
JC, JNC, JN, JGE, JL
Conditional Bit Test and Branch BTJT, BTJF
ATmega32A. 8-bit Microcontroller with 32K Bytes In-System
Programmable Flash. Atmel, 8155A AVR 06/08, p.336
C51 Instruction Set (111 Instructions)
ST7 Instruction Set (63 Instructions)
MSP430 Core Instruction Set (27 Instructions)
ATmega32 Instruction Set (132 Instructions) 1/2
MCU control NOP, SLEEP, WDR, BREAK
Load and Transfer MOV, MOVW, LDI, LD, LDD, LDS,
CLR, SET, ST, STD, STS, LPM, SPM,
data
IN, OUT
transfer
Stack operation PUSH, POP
Logical operations AND, ANDI, OR, ORI, EOR,
COM, NEG
Shift and Rotates LSL, LSR, ROL, ROR, ASR, SWAP
logic
Bit operations BSET, SBI, SBR, BCLR, CBI, CBR,
BST, BLD, SEC, CLC, SEN, CLN,
SEZ, CLZ, SES, CLS, SEV, CLV,
SET, CLT, SEH, CLH
ATmega32A. 8-bit Microcontroller with 32K Bytes In-System
Programmable Flash. Atmel, 8155A AVR 06/08, p.336
C51 Instruction Set (111 Instructions)
ST7 Instruction Set (63 Instructions)
MSP430 Core Instruction Set (27 Instructions)
ATmega32 Instruction Set (132 Instructions) 2/2
Arithmetic operations ADD, ADC, ADIW,
SUB, SUBI, SBC, SBCI, SBIW,
MUL, MULS, MULSU, FMUL,
arithmetic
FMULS, FMULSU
Increment/Decrement INC, DEC
Compare and Tests TST, CPSE, CP, CPC, CPI
Interruption management SIE, CLI, RETI, BRIE, BRID
Unconditional Jump or Call RJMP, IJMP, JMP,
RCALL, ICALL, CALL, RET
control
Conditional Branch BRBC, BREQ, BRNE,
transfer
BRCS, BRCC, BRSH, BRLO, BRMI,
BRPL, BRGE, BRLT, BRHS, BRHC,
BRTS, BRTC, BRVS, BRVC
Conditional Bit Test and Branch SBRC, SBRS, SBIC, SBIS, BRBS
UM10344. P89LPC9151/9161/9171 User manual.
NXP Semiconductors, 7 January 2010, Rev. 01, p/128-129
C51
Logical Operations
ANL arg_1, arg_2 ; arg_1 �! arg_1 AND arg_2
ORL arg_1, arg_2 ; arg_1 �! arg_1 OR arg_2
XRL arg_1, arg_2 ; arg_1 �! arg_1 XOR arg_2
1, 2 Cycles
CPL A ; A �! NOT A
(Standard)
A7..A4 A3..A0
SWAP A ; Swap Nibbles of A
RL A ; Rotate A left
A7 A0
A7 A0
C
RLC A ; Rotate A left through carry
A7 A0
RR A ; Rotate A right
A7 A0
RRC A ; Rotate A right through carry
C
Maskowanie bitów
wyzerować podane bity akumulatora A: A6, A5, A2 i A0.
akumulator A: 7 6 5 4 3 2 1 0
Maska EQU 0110 0101b
; deklaracja bitów maski
;maska: 0 1 1 0 0 1 0 1
Zerowanie_bitów: ANL A, #NOT Maska ; A �! A AND NOT maska
Ustawianie_bitow: ORL A, #Maska ; A �! A OR maska
Negacja_bitow: XRL A, #Maska ; A �! A XOR maska
MSP430 - Logical Operations
AND(.B) src,dst ; src .and. dst dst
BIT(.B) src,dst ; src .and. dst
BIC(.B) src,dst ; .not.src .and. dst dst
BIS(.B) src,dst ; src .or. dst dst
XOR(.B) src,dst ; src .xor. dst dst
*INV[.B] dst ; .NOT.dst dst
; Invert destination, Emulation XOR #0FFFFh,dst
SWPB dst Swap bytes
SXT dst Bit 7 Bit 8........Bit 15
*RLA(.B) dst ; C �! MSB �! MSB-1 .... LSB+1 �! LSB �! 0
; Rotate left arithmetically, Emulation ADD dst,dst
*RLC(.B) dst ; C <- MSB <- MSB-1 .... LSB+1 <- LSB <- C
; Rotate left through carry, Emulation ADDC dst,dst
RRA(.B) dst MSB MSB ....LSB C
RRC(.B) dst C MSB .......LSB C
Shift operations (1/2)
N
K K-1
0
MSP430: SXT dst
Before:
Extend sign, the
sign of the LOW byte
N
K K-1
0
is extended into the
After:
HIGH byte
N
K K-1
0
Before:
N
K K-1
0
After:
C51 ST7 MSP430
SWAP A SRA reg [mem] SWPB dst
Shift operations (2/2)
C51 ST7 MS430
N 0
dstN ... dst0
RR A ??? ???
N 0
dstN ... dst0 C
0 ??? SRL reg [mem] ???
N 0
RRC A RRC reg [mem] RRC dst
C
dstN ... dst0
N 0
??? SRA reg [mem] RRA dst
dstN ... dst0 C
C51: Wielobajtowe przesuwanie bitów
przykład: przesunąć binarnie (podzielić przez 2) 2-bajtową zmienną
zawartą w rejestrach: R7 (MSB) i R6 (LSB).
R7: R6:
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
C
C = ? C
Przesun_2_bajty:
MOV A, R7 ; A �! R7
RRC A ; C A7 A6 .. A1 A0 C
MOV R7, A ; R7 �! A
MOV A, R6 ; A �! R6
RRC A ; C A7 A6 .. A1 A0 C
MOV R6, A ; R6 �! A
ARM7
Logical Operations
AND Rd := Rn AND shifter_operand
TST ONLY Update flags after Rn AND shifter_operand Test
BIC Rd := Rn AND NOT(shifter_operand) Bit Clear
ORR Rd := Rn OR shifter_operand
EOR Rd := Rn EOR shifter_operand Exclusive OR
TEQ ONLY Update flags after Rn EOR shifter_operand Test Equivalence
Example:
j = 0x12345678; LDR R0, [PC, #0x0074] ; R0 = 0x1234 5678
j = (j >> 4) & 0x3FF; LDR R1, [PC, #0x0074] ; R1 = 0x0000 03FF
AND R0, R1, R0, ASR #4 ; R0 = 0x0000 0167
A[31:0] control
Address register
ARM7
P P
incrementer
C C
Barrel shifter (1/2)
Register
bank
ability to shift the 32-bit binary
A
pattern in one source registers
L
Instruction
U
left or right by a specific number
decode
A
of positions before it enters the
mult
b
&
u
ALU
b
control
B
s
u
shifting increases the power and s
Barrel
b
flexibility of many data processing
shifter
u
operations s
ALU
5 different shift operations:
logical shift left LSL
logical shift right LSR
arithmetic shift right ASR
rotate right ROR
Data out register Data in register
rotate right extended RRX
ARM7
5 different shift operations
LSL - Logical Shift Left by n bits
CF destination
0
(multiplication by 2n)
LSR - Logical Shift Right by n bits
destination CF
0
(unsigned division by 2n)
ASR - Arithmetic Shift Right by n bits; the
bits fed into the top end of the operand are
destination CF
copies of the original top-or sign-bit
(signed division by 2n)
destination CF
ROR - ROtate Right by n bits
destination CF
RRX - Rotate Right eXtended only by 1 bit
Barrel
shifter
ARM7
Barrel shifter
ALU
Steve Furber: ARM System-on-chip Architecture. p92
principle of the cross-bar switch - 4 x 4 matrix,
ARM use a 32 x 32 matrix
no shift
right 1
right 3 right 2
each switch is a single NMOS
in[3]
transistor
left 1
each input is connected to each
in[2]
left 2
output through a switch - if pre-
in[1]
charged dynamic logic is used, as
left 3
it is on the ARM datapaths
in[0]
shifting functions are
implemented by wiring switches
along diagonals to a common
out[0] out[1] out[2] out[3]
control input
ARM7
Left or right shift
for a left or right shift
function, one diagonal is
in[3..0] = 1100
turned on
no shift
right 1
right 3 right 2
this connects all the input
in[3] = 1
bits to their respective
left 1
outputs where they are used
in[2] = 1
left 2
not all are used, since some
in[1] = 0
bits 'fall off the end
left 3
in the ARM the barrel shifter in[0] = 0
operates in negative logic
where a ' 1' is represented as
a potential near ground and a
out[0] out[1] out[2] out[3]
'0' by a potential near the
supply - precharging sets all
the outputs to a logic '0', so
shift left 1 "! out[3..0] = 1000
"!
"!
"!
those outputs that are not
shift right 1 "! out[3..0] = 0110
"!
"!
"!
connected to any input
Format instrukcji - C51 (1/3)
rozkazy 1- bajtowe, 2-bajtowe i 3-bajtowe
kod rozkazu bez argumentów lub z pojedynczym, ukrytym argumentem:
0 0 0 0 0 0 0 0 np. NOP
1 0 0 1 0 0 1 1 np. MOVC A, @A+DPTR
kod rozkazu i argumenty:
1 bit dla adresowania pośredniego:
1 1 1 0 0 1 1 i np. MOV A, @Ri
3 bity dla adresowania rejestrowego:
1 1 1 0 1 r r r np. MOV A, Rn
Format instrukcji - C51 (2/3)
rozkazy 1-bajtowe, 2- bajtowe i 3- bajtowe
kod rozkazu i argumenty:
2 bajty dla adresowania bezpośredniego:
1 1 1 1 0 1 0 1
np. MOV addr, A
addr
3 bajty dla dwóch 1-bajtowych argumentów:
1 0 1 1 0 1 0 1
addr np. CJNE A, addr, rel
rel
Format instrukcji - C51 (3/3)
rozkazy 1-bajtowe, 2-bajtowe i 3-bajtowe
kod rozkazu i argumenty:
3 bajty dla jednego, 2-bajtowego argumentu:
0 0 0 1 0 0 1 0
addr_1615..8
np. CALL addr_16
addr_167..0
Format rozkazu wykorzystujący różne podane kombinacje:
1 0 1 1 1 r r r
data
np. CJNE Rn, #data, rel
rel
PREFIX w kodach rozkazów C51
x0 x1 x2 x3 x5
AJMP LJMP RR INC
0x NOP
addr16
addr11 A addr
OPCODE
JBC ACALL LCALL RRC DEC
PREFIX = 0A5h
1x
addr16
bit, rel addr11 A addr
dodatkowe
JB AJMP RL ADD
instrukcje np.
2x RET
bit, rel addr11 A A, addr
80C51MX (Philips)
C251 (Intel/Atmel)
ORL AJMP MOV INC OPCODE
Ax
C, /bit addr11 C, bit DPTR PREFIX
POP ACALL LJMP RR DJNZ Brak
Dx
addr addr11 addr16 A addr, rel instrukcji:
MOVX AJMP MOVX MOV dla CODE
Ex
A,@DPTR A, @Ri
addr11 A, addr do 2KB
MOVX ACALL MOVX MOV
Fx
@DPTR,A @Ri, A
addr11 addr, A bez P0 i P2
Format instrukcji - PIC16C77x (Microchip Techn.)
stała długość instrukcji równa 14-bitów
Byte-
13 8 7 6 0
oriented
OP-Code d f (FILE #)
file register
operations:
d = 0 for destination W (Working register - accumulator)
d = 1 for destination f (register file address: 0 .. 7Fh)
f = 7-bit file register address (0 .. 7Fh)
Bit-oriented
13 10 9 7 6 0
file register
OP-Code b (BIT #) f (FILE #)
operations:
b = 3-bit address (bit address within an 8-bit file register)
f = 7-bit register address (0 .. 7Fh)
13 11 10 0
CALL and
k (literal)
OP-Code
GOTO
instructions
k = 11-bit immediate value (label a" address)
MSP430x4xx Family User s Guide.
Texas Instruments, SLAU056G, 2007, p.3-18
Procesory RISC
MSP430  formaty rozkazów
15 12 11 8 7 6 5 4 3 0
OP - Code source register Ad B/W As dest. register Format I
As/Ad Addressing Mode
15 12 11 7 6 5 4 3 0
0 0 0 1 OP - Code B/W Ad dest. register Format II
Ad Addressing Mode
15 13 12 10 9 8 0
0 0 1 OP - Code S Offset Format III
Contitional and unconditional Jumps (+/ 9 bit Offset)
ARM7DI Data Sheet. ARM DDI 0027D, Dec 1994, p.25
CPSR / SPSR
31 28 0
ARM7
N Z C V
Instruction Set
Addressing Modes
C500. Architecture and Instruction Set. User s MANUAL.
Infineon, July 200, p.4-1
ST7 FAMILY PROGRAMMING MANUAL. STMicroelectronics, November 2005
MSP430x1xx Family User s Guide. Texas Instruments, SLAU049F, 2006
8-bit AVR Instruction Set. Atmel, Rev. 0856G AVR 07/08
ARM Architecture Reference Manual. ARM DDI 0100E, June 2000
Addressing Modes
Immediate (1/2)
allows constants to be part of the instruction in program memory:
ANL P1, #01110011B ; C51: P1 �! P1 and 01110011b
; clear bits 7, 3, and 2 of output port P1
add A, #$15 ; ST7: A �! A + $15
ldi r17, 0xFF ; AVR: R17 �! 0FFh
dadd.w #0x9876, R5 ; MSP430: 9876h + R5 + C R5
; (decimally)
SWI{} ; ARM7: SWI (Software Interrupt)
; value is ignored by the ARM processor,
; but can be used by an operating system SWI exception
; handler to determine what operating system service is
; being requested
C500. Architecture and Instruction Set. User s MANUAL.
Infineon, July 2000, p.4-18
Addressing Modes
Immediate (2/2)
allows constants to be part of the instruction in program memory:
ANL P1, #01110011B ; P1 �! P1 and 01110011b
; clear bits 7, 3, and 2 of output port P1
...........
addr  1
addr
OpCode = 53h
0101 0011
addr + 1
1001 0000 P1 = 90h = 1001 0000
Constant = 73h
addr + 2 0111 0011
...........
addr + 3
0
...........
addr + 4 7 3 2
P1 x x x x x x x x
Program
Memory
Constant 0 1 1 1 0 0 1 1
and
P1 0 x x x 0 0 x x
Addressing Modes
Register
accesses the working registers:
ANL B, #01110011B ; C51: B �! B and 01110011b
add A, #$15 ; ST7: A �! A + $15
ldi r17, 0xFF ; AVR: R17 �! 0FFh
dadd.w #0x9876, R5 ; MSP430: 9876h + R5 + C R5
; (decimally)
MOV R2, R0, LSL #2 ; ARM7: Shift R0 left by 2, write to R2
; (R2 = R0 " 4)
C500. Architecture and Instruction Set. User s MANUAL.
Infineon, July 200, p.4-1
0xxh
C51 Addressing Modes
external
Register
RAM
0FFh
SFR RAM
300h
80h
7Fh 256-byte
accesses the eight working
200h
RAM
registers (R0 - R7) of the
256-byte
selected register bank  1Fh 100h
R7
R7
least significant bit of the
256-byte
R6R7
RB3
R6R7
0
instruction opcode indicates
R5R6
R5R6
R4R5
which register is to be used. RB2 C51 Core
R4R5
R3R4
ACC, B, DPTR and CY, the R3R4
RB1
R2R3
R2R3
Boolean processor
R1R2
R1R2
RB0
accumulator, can also be
R0R1 B A temp
R0R1
R0
addressed as registers
R0
0
ALU
PSW
DPTR
Addressing Modes
Direct
address is a byte or word, thus require only one byte or word after the
op-code:
ANL P1, #01110011B ; C51: (P1) �! (P1) and 01110011b
ld A, $4B ; ST7: A �! ($4B)
lds r12, 0x00FF ; AVR: R12 �! (00FFh)
; MSP430 ;
LDR PC, Reset_Addr ; ARM7: PC �! (Reset_Addr)
C500. Architecture and Instruction Set. User s MANUAL.
Infineon, July 200, p.4-1
0xxh
C51 Addressing Modes
external
Direct
RAM
0FFh
SFR
RAM
300h
80h
7Fh 256-byte
200h
RAM
256-byte
1Fh 100h
R7
R7
256-byte
R6R7
RB3
only method of accessing
R6R7
0
R5R6
R5R6
the special function registers
R4R5
RB2 C51 Core
R4R5
SFR
R3R4
R3R4
RB1
R2R3
R2R3
R1R2
lower 128 bytes of internal
R1R2
RB0
R0R1 B A temp
RAM
R0R1
R0
R0
0
ALU
PSW
DPTR
ST7 FAMILY PROGRAMMING MANUAL.
STMicroelectronics, November 2005, p.12-13
ST7 Addressing Modes
Short / Long Direct
allows constants to be part of the instruction in program memory:
LDA A, $4B ; A �! ($4B),
; Short Direct, 0..FF addressing space
LDA A, $06E5 ; A �! ($06E5),
; Long Direct, 0..FFFF addressing space
..........
addr  1
..........
addr  1
addr
OpCode
$C6
addr
OpCode
$B6
addr + 1
$06
Coeff addr
addr + 1
$4B
Coeff addr
addr + 2 $E5
..........
addr + 2
..........
addr + 3
..........
..........
..........
$004B  1
..........
$06E5  1
Coeff
$004B $20
Coeff
$06E5 $40
..........
$004B + 1
..........
$06E5 + 1
A
A
Memory
Memory
Addressing Modes
Indirect
operand address is a register or pointer contens:
ADD A, @R1 ; C51: A �! A + (R1), only R0, R1
cp A, [ptr] ; ST7: Reg CC: {N, Z, C} �! A  ((ptr))
ld r10, X ; AVR: R10 �! (X),
; Loads one byte indirect from the data
; space (X or Y or Z) to a register Rd
cmp @r6, r7 ; MSP430: Reg SR: {N, Z, C, V} �! r7  (r6)
STR R3, [R2] ; ARM7: [R2] �! R3,
; store word from R3 to the address in R2
C500. Architecture and Instruction Set. User s MANUAL.
Infineon, July 200, p.4-1
0xxh
C51 Addressing Modes
external
Indirect
RAM
0FFh
SFR
RAM
300h
80h
7Fh 256-byte
200h
RAM
256-byte
1Fh 100h
R7
R7
256-byte
R6R7
RB3
R6R7
0
uses contents of either
R5R6
R5R6
R0 or R1 (in the selected
R4R5
RB2 C51 Core
R4R5
register bank)
R3R4
R3R4
RB1
R2R3
R2R3
R0 or R1 is a pointer to
R1R2
R1R2
RB0
locations in a 256-byte
R0R1 B A temp
R0R1
R0
block internal of RAM
R0
0
R0 or R1 is a pointer to
locations in a 256-byte ALU
PSW
block of external RAM
DPTR
(256"
"P2 + Ri)
"
"
MSP430x1xx Family User s Guide.
Texas Instruments, SLAU049F, 2006, p.3-15
MSP430 Addressing Modes
Indirect and ???
indirect autoincrement:
MOV.W @R10+, R11 ; (R10) R11
; R10 + 2 R10, post incremented
; Move the contents of the source address (contents of R10) to
; the destination register R11. Register R10 is incremented by
; 1 for a byte operation, or 2 for a word operation after the fetch;
; it points to the next address without any overhead  useful for
; table processing
8-bit AVR Instruction Set.
Atmel, Rev. 0856G AVR 07/08, p.85
AVR Addressing Modes
Indirect and ???
loads one byte indirect with or without displacement from the data space
to a register
" indirect post-autoincrement
LD R13, Y+ ; R13 �! (Y)
; Y �! Y + 1, post incremented
" indirect pre-autodecrement
LD R13,  Y ; Y �! Y  1, pre decremented
; R13 �! (Y)
" indirect with displacement
LD R13, Y + 48 ; R13 �! (Y + 48)
features are especially suited for accessing arrays, tables, and Stack
Pointer usage of the Y-pointer Register
Addressing Modes
Indexed
MOVC A, @A+DPTR ; C51: A �! (A + DPTR)CODE
LD A, ([ptr.w], X) ; ST7: A �! ([ptr.word], X)
LD Rd, X ; AVR: Load Indirect from Data Space
LD Rd, X+ ; to Register using Index X
LD Rd,  X
MOV 2(R5), 6(R6) ; MSP430: (2 + (R5)) (6 + (R6))
LDRcc R0, [R1, #12] ! ; ARM7: if cc = true then R1 = R1 + 12
; R0 �! (R1 + 12), pre-indexed
LDRcc R0, [R1], #12 ; ARM7: R0 �! (R1), post-indexed
; if cc = true then R1 = R1 + 12
ST7 FAMILY PROGRAMMING MANUAL.
STMicroelectronics, November 2005, p.21-25
ST7 Addressing Modes
Indirect indexed
loads one byte indirect with or without displacement from the data space to a
register
" Short / Long indirect indexed
(pointer address is a byte, the pointer size is a byte / word)
LD A, ([ptr.w], X) ; A �! ([ptr.word], X)
Example:
0089 0800 ptr dc.wtable
2
1
0800 10203040 table dc.b$10,$20,$30,$40
3
0800+3
4
0690 AE03 ld X, #3 ; X = 3
0692 92D689 ld A, ([ptr.w], X) ; A �! ([ptr.w], X) =
; (($89.w), 3) = 1
; ($0800,3) =
2
; ($0803) =
3
; $40
4
MSP430x1xx Family User s Guide.
Texas Instruments, SLAU049F, 2006, p.3-11
MSP430 Addressing Modes
Indexed
Address
Space
MOV #01080h, R5 ; 01080h R5
..........
0FF18h
MOV #0108Ch, R6 ; 0108Ch R6
0FF16h
00006h
MOV 2(R5), 6(R6) ; (2 + (R5)) (6 + (R6)) 0FF14h
00002h
0FF12h 04596h PC
..........
0FF10h
R6 = 0108Ch
+0006h
..........
01094h
01092h
01092h
05555h
..........
01090h
R5 = 01080h
+0002h
..........
01084h
01082h
01082h
01234h
..........
01080h
MSP430x1xx Family User s Guide.
Address
Texas Instruments, SLAU049F, 2006, p.3-12..13
Space
..........
MSP430 Addressing Modes
0FF18h
0FF16h 011FEh
Symbolic, Absolute
0FF14h
0F102h
0FF12h 04090h
MOV EDE, TONI ; MOV X(PC), Y(PC)
..........
0FF10h
; X = EDE - PC,
; Y = TONI - PC
0FF14h
+0F102h
..........
0F018h
; Src addr EDE = 0F016h
; Dst addr TONI = 01114h
0F016h
0F016h 0A123h
..........
0F014h
0FF16h
Relative Addressing
+011FEh
..........
01116h
01114h
01114h 05555h
..........
01112h
MOV &EDE, &TONI ; MOV X(0),Y(0)
; X = EDE
; Y = TONI
; Src addr EDE=0F016h,
; Dst addr TONI=01114h
Symbolic mode
Absolute mode
Addressing Modes
Relative
DJNZ Rn, rel ; C51: Rn �! Rn  1
; if Rn = 0 then PC �! PC + rel
JRcc label ; ST7: if (cc == 1) then
; PC = PC + oft
; or PC = PC + (oft)
; else PC = PC
RJMP k ; AVR: PC �! PC + k + 1
;  2K d" k < 2K
MOV EDE, TONI ; MSP430: MOV X(PC), Y(PC)
; X = EDE - PC
; Y = TONI - PC
LDR Rd,=const ; ARM7: LDR Rn, [PC, #offset to literal pool]
; load Rn register with one word
; from the address [PC + offset]
Memory Addressing Mode 2
Load and Store Word or Unsigned Byte
LDR|STR{}{B}{T} ,
where is one of the nine options for Word or Unsigned
Byte:
[, #+/-] Immediate offset
[, +/-] Register offset
[, +/-, #] Scaled register offset
[, #+/-]! Immediate pre-indexed
[, +/-]! Register pre-indexed
[, +/-, #]! Scaled register pre-indexed
[], #+/- Immediate post-indexed
[], +/- Register post-indexed
[], +/-, # Scaled register post-indexed
Offset or Pre or Post Memory Addressing (1/2)
Offset-addressing modes  the memory address is formed by adding or
subtracting an offset:
- immediate offset / index
LDR Rd, [, #+/ ] ; Rd �! (Rn +/ offset_12)
�!
�!
�!
- register offset / index
LDR Rd, [, +/ ] ; Rd �! (Rn +/ Rm)
�!
�!
�!
- scaled register offset / index
LDR Rd, [, +/ , Barrel_shifter #]
; Rd �! (Rn +/ Barrel_shifter )
�!
�!
�!
example immediate offset-addressing:
LDR R0, [R1, #12] ; R0 �! (R1 + 12)
�!
�!
�!
0x12
0x20C
12 0x12
Offset
R0
R1
Base
0x200
0x45
Register 0x200
Offset or Pre or Post Memory Addressing (2/2)
Pre-indexed: LDR R0, [R1, #12] ! ; R0 �! (R1 + 12)
�!
�!
�!
; if cc = true then R1 = R1 + 12
R1 Offset
Updated
0x12
0x20C
0x20C 12
0x12
Base Register
R0
R1
Base
0x45
0x200
0x200
Register
Post-indexed: LDR R0, [R1], #12 ; R0 �! (R1)
�!
�!
�!
; if cc = true then R1 = R1 + 12
R1
Offset
Updated
0x12
0x20C
0x20C 12
Base Register
R0
R1
Original
0x5 0x45
0x45
0x200
0x200
Base Register
write back


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