3axis Digital Accelerometer ADXL345

3-Axis, ą2 g/ą4 g/ą8 g/ą16 g
Digital Accelerometer
ADXL345
FEATURES GENERAL DESCRIPTION
Ultralow power: as low as 23 �A in measurement mode and The ADXL345 is a small, thin, ultralow power, 3-axis accelerometer
0.1 �A in standby mode at V = 2.5 V (typical) with high resolution (13-bit) measurement at up to ą16 g. Digital
S
Power consumption scales automatically with bandwidth output data is formatted as 16-bit twos complement and is acces-
User-selectable resolution sible through either a SPI (3- or 4-wire) or I2C digital interface.
Fixed 10-bit resolution
The ADXL345 is well suited for mobile device applications. It
Full resolution, where resolution increases with g range,
measures the static acceleration of gravity in tilt-sensing appli-
up to 13-bit resolution at ą16 g (maintaining 4 mg/LSB
cations, as well as dynamic acceleration resulting from motion
scale factor in all g ranges)
or shock. Its high resolution (3.9 mg/LSB) enables measurement
Patent pending, embedded memory management system
of inclination changes less than 1.0�.
with FIFO technology minimizes host processor load
Several special sensing functions are provided. Activity and
Single tap/double tap detection
inactivity sensing detect the presence or lack of motion by
Activity/inactivity monitoring
comparing the acceleration on any axis with user-set thresholds.
Free-fall detection
Tap sensing detects single and double taps in any direction. Free-
Supply voltage range: 2.0 V to 3.6 V
fall sensing detects if the device is falling. These functions can
I/O voltage range: 1.7 V to V
S
be mapped individually to either of two interrupt output pins.
SPI (3- and 4-wire) and I2C digital interfaces
An integrated, patent pending memory management system with a
Flexible interrupt modes mappable to either interrupt pin
32-level first in, first out (FIFO) buffer can be used to store data to
Measurement ranges selectable via serial command
minimize host processor activity and lower overall system power
Bandwidth selectable via serial command
consumption.
Wide temperature range (-40�C to +85�C)
10,000 g shock survival
Low power modes enable intelligent motion-based power
Pb free/RoHS compliant
management with threshold sensing and active acceleration
Small and thin: 3 mm � 5 mm � 1 mm LGA package
measurement at extremely low power dissipation.
APPLICATIONS
The ADXL345 is supplied in a small, thin, 3 mm � 5 mm � 1 mm,
14-lead, plastic package.
Handsets
Medical instrumentation
Gaming and pointing devices
Industrial instrumentation
Personal navigation devices
Hard disk drive (HDD) protection
FUNCTIONAL BLOCK DIAGRAM
VS VDD I/O
ADXL345
POWER
MANAGEMENT
INT1
CONTROL
SENSE AND
ADC
DIGITAL
ELECTRONICS INTERRUPT
FILTER
3-AXIS LOGIC
INT2
SENSOR
SDA/SDI/SDIO
32 LEVEL
SERIAL I/O
FIFO SDO/ALT
ADDRESS
SCL/SCLK
GND CS
Figure 1.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Tel: 781.329.4700 www.analog.com
Trademarks and registered trademarks are the property of their respective owners. See the last
page for disclaimers. Fax: 781.461.3113 �2009 2011 Analog Devices, Inc. All rights reserved.
07925-001
ADXL345
TABLE OF CONTENTS
Self-Test ....................................................................................... 22
Features .............................................................................................. 1
Register Map ................................................................................... 23
Applications....................................................................................... 1
Register Definitions ................................................................... 24
General Description ......................................................................... 1
Applications Information .............................................................. 28
Functional Block Diagram .............................................................. 1
Power Supply Decoupling ......................................................... 28
Revision History ............................................................................... 3
Mechanical Considerations for Mounting.............................. 28
Specifications..................................................................................... 4
Tap Detection.............................................................................. 28
Absolute Maximum Ratings............................................................ 6
Threshold .................................................................................... 29
Thermal Resistance ...................................................................... 6
Link Mode ................................................................................... 29
Package Information .................................................................... 6
Sleep Mode vs. Low Power Mode............................................. 30
ESD Caution.................................................................................. 6
Offset Calibration....................................................................... 30
Pin Configuration and Function Descriptions............................. 7
Using Self-Test ............................................................................ 31
Typical Performance Characteristics ............................................. 8
Data Formatting of Upper Data Rates..................................... 32
Theory of Operation ...................................................................... 13
Noise Performance..................................................................... 33
Power Sequencing ...................................................................... 13
Operation at Voltages Other Than 2.5 V ................................ 33
Power Savings ............................................................................. 14
Offset Performance at Lowest Data Rates............................... 34
Serial Communications ................................................................. 15
Axes of Acceleration Sensitivity ............................................... 35
SPI................................................................................................. 15
Layout and Design Recommendations ................................... 36
I2C ................................................................................................. 18
Outline Dimensions ....................................................................... 37
Interrupts..................................................................................... 20
Ordering Guide .......................................................................... 37
FIFO ............................................................................................. 21
Rev. C | Page 2 of 40
ADXL345
REVISION HISTORY
5/11 Rev. B to Rev. C Added Table 13................................................................................19
Added Preventing Bus Traffic Errors Section ............................15 Changes to FIFO Section ...............................................................20
Changes to Figure 37, Figure 38, Figure 39 .................................16 Changes to Self-Test Section and Table 15 to Table 18 ..............21
Changes to Table 12 ........................................................................19 Added Figures 42 and Table 14 .....................................................21
Changes to Using Self-Test Section...............................................31 Changes to Table 19 ........................................................................22
Changes to Axes of Acceleration Sensitivity Section..................35 Changes to Register 0x1D THRESH_TAP (Read/Write)
Section, Register 0x1E, Register 0x1F, Register 0x20 OFSX,
11/10 Rev. A to Rev. B
OFSY, OSXZ (Read/Write) Section, Register 0x21 DUR
Change to 0 g Offset vs. Temperature for Z-Axis Parameter,
(Read/Write) Section, Register 0x22 Latent (Read/Write)
Table 1 .................................................................................................4
Section, and Register 0x23 Window (Read/Write) Section ...23
Changes to Figure 10 to Figure 15 ..................................................9
Changes to ACT_X Enable Bits and INACT_X Enable Bit
Changes to Ordering Guide...........................................................37
Section, Register 0x28 THRESH_FF (Read/Write) Section,
4/10 Rev. 0 to Rev. A
Register 0x29 TIME_FF (Read/Write) Section, Asleep Bit
Changes to Features Section and General
Section, and AUTO_SLEEP Bit Section.......................................24
Description Section...........................................................................1
Changes to Sleep Bit Section .........................................................25
Changes to Specifications Section...................................................3
Changes to Power Supply Decoupling Section, Mechanical
Changes to Table 2 and Table 3 .......................................................5
Considerations for Mounting Section, and Tap Detection
Added Package Information Section, Figure 2, and Table 4;
Section ..............................................................................................27
Renumbered Sequentially ................................................................5
Changes to Threshold Section.......................................................28
Changes to Pin 12 Description, Table 5 .........................................6
Changes to Sleep Mode vs. Low Power Mode Section...............29
Added Typical Performance Characteristics Section ...................7
Added Offset Calibration Section.................................................29
Changes to Theory of Operation Section and Power Sequencing
Changes to Using Self-Test Section ..............................................30
Section ..............................................................................................12
Added Data Formatting of Upper Data Rates Section, Figure 48,
Changes to Powers Savings Section, Table 7, Table 8, Auto Sleep
and Figure 49 ...................................................................................31
Mode Section, and Standby Mode Section ..................................13
Added Noise Performance Section, Figure 50 to Figure 52, and
Changes to SPI Section...................................................................14
Operation at Voltages Other Than 2.5 V Section .......................32
Changes to Figure 36 to Figure 38 ................................................15
Added Offset Performance at Lowest Data Rates Section and
Changes to Table 9 and Table 10 ...................................................16
Figure 53 to Figure 55.....................................................................33
Changes to I2C Section and Table 11 ............................................17
6/09 Revision 0: Initial Version
Changes to Table 12 ........................................................................18
Changes to Interrupts Section, Activity Section, Inactivity
Section, and FREE_FALL Section.................................................19
Rev. C | Page 3 of 40
ADXL345
SPECIFICATIONS
T = 25�C, V = 2.5 V, V = 1.8 V, acceleration = 0 g, C = 10 �F tantalum, C = 0.1 �F, output data rate (ODR) = 800 Hz, unless
A S DD I/O S I/O
otherwise noted. All minimum and maximum specifications are guaranteed. Typical specifications are not guaranteed.
Table 1.
Parameter Test Conditions Min Typ1 Max Unit
SENSOR INPUT Each axis
Measurement Range User selectable ą2, ą4, ą8, ą16 g
Nonlinearity Percentage of full scale ą0.5 %
Inter-Axis Alignment Error ą0.1 Degrees
Cross-Axis Sensitivity2 ą1 %
OUTPUT RESOLUTION Each axis
All g Ranges 10-bit resolution 10 Bits
ą2 g Range Full resolution 10 Bits
ą4 g Range Full resolution 11 Bits
ą8 g Range Full resolution 12 Bits
ą16 g Range Full resolution 13 Bits
SENSITIVITY Each axis
Sensitivity at X , Y , Z All g-ranges, full resolution 230 256 282 LSB/g
OUT OUT OUT
ą2 g, 10-bit resolution 230 256 282 LSB/g
ą4 g, 10-bit resolution 115 128 141 LSB/g
ą8 g, 10-bit resolution 57 64 71 LSB/g
ą16 g, 10-bit resolution 29 32 35 LSB/g
Sensitivity Deviation from Ideal All g-ranges ą1.0 %
Scale Factor at X , Y , Z All g-ranges, full resolution 3.5 3.9 4.3 mg/LSB
OUT OUT OUT
ą2 g, 10-bit resolution 3.5 3.9 4.3 mg/LSB
ą4 g, 10-bit resolution 7.1 7.8 8.7 mg/LSB
ą8 g, 10-bit resolution 14.1 15.6 17.5 mg/LSB
ą16 g, 10-bit resolution 28.6 31.2 34.5 mg/LSB
Sensitivity Change Due to Temperature ą0.01 %/�C
0 g OFFSET Each axis
0 g Output for X , Y -150 0 +150 mg
OUT OUT
0 g Output for Z -250 0 +250 mg
OUT
0 g Output Deviation from Ideal, X , Y ą35 mg
OUT OUT
0 g Output Deviation from Ideal, Z ą40 mg
OUT
0 g Offset vs. Temperature for X-, Y-Axes ą0.4 mg/�C
0 g Offset vs. Temperature for Z-Axis ą1.2 mg/�C
NOISE
X-, Y-Axes ODR = 100 Hz for ą2 g, 10-bit resolution or 0.75 LSB rms
all g-ranges, full resolution
Z-Axis ODR = 100 Hz for ą2 g, 10-bit resolution or 1.1 LSB rms
all g-ranges, full resolution
OUTPUT DATA RATE AND BANDWIDTH User selectable
Output Data Rate (ODR)3, 4, 5 0.1 3200 Hz
SELF-TEST6
Output Change in X-Axis 0.20 2.10 g
Output Change in Y-Axis -2.10 -0.20 g
Output Change in Z-Axis 0.30 3.40 g
POWER SUPPLY
Operating Voltage Range (V ) 2.0 2.5 3.6 V
S
Interface Voltage Range (V ) 1.7 1.8 V V
DD I/O S
Supply Current ODR e" 100 Hz 140 �A
ODR < 10 Hz 30 �A
Standby Mode Leakage Current 0.1 �A
Turn-On and Wake-Up Time7 ODR = 3200 Hz 1.4 ms
Rev. C | Page 4 of 40
ADXL345
Parameter Test Conditions Min Typ1 Max Unit
TEMPERATURE
Operating Temperature Range -40 +85 �C
WEIGHT
Device Weight 30 mg
1
The typical specifications shown are for at least 68% of the population of parts and are based on the worst case of mean ą1 �, except for 0 g output and sensitivity,
which represents the target value. For 0 g offset and sensitivity, the deviation from the ideal describes the worst case of mean ą1 �.
2
Cross-axis sensitivity is defined as coupling between any two axes.
3
Bandwidth is the -3 dB frequency and is half the output data rate, bandwidth = ODR/2.
4
The output format for the 3200 Hz and 1600 Hz ODRs is different than the output format for the remaining ODRs. This difference is described in the Data Formatting of
Upper Data Rates section.
5
Output data rates below 6.25 Hz exhibit additional offset shift with increased temperature, depending on selected output data rate. Refer to the Offset Performance at
Lowest Data Rates section for details.
6
Self-test change is defined as the output (g) when the SELF_TEST bit = 1 (in the DATA_FORMAT register, Address 0x31) minus the output (g) when the SELF_TEST bit =
0. Due to device filtering, the output reaches its final value after 4 � � when enabling or disabling self-test, where � = 1/(data rate). The part must be in normal power
operation (LOW_POWER bit = 0 in the BW_RATE register, Address 0x2C) for self-test to operate correctly.
7
Turn-on and wake-up times are determined by the user-defined bandwidth. At a 100 Hz data rate, the turn-on and wake-up times are each approximately 11.1 ms. For
other data rates, the turn-on and wake-up times are each approximately � + 1.1 in milliseconds, where � = 1/(data rate).
Rev. C | Page 5 of 40
ADXL345
ABSOLUTE MAXIMUM RATINGS
PACKAGE INFORMATION
Table 2.
Parameter Rating The information in Figure 2 and Table 4 provide details about
the package branding for the ADXL345. For a complete listing
Acceleration
of product availability, see the Ordering Guide section.
Any Axis, Unpowered 10,000 g
Any Axis, Powered 10,000 g
V -0.3 V to +3.9 V
S
V -0.3 V to +3.9 V
DD I/O
Digital Pins -0.3 V to V + 0.3 V or 3.9 V,
DD I/O
3 4 5 B
whichever is less
All Other Pins -0.3 V to +3.9 V
# y w w
Output Short-Circuit Duration Indefinite
(Any Pin to Ground)
v v v v
Temperature Range
Powered -40�C to +105�C
C N T Y
Storage -40�C to +105�C
Stresses above those listed under Absolute Maximum Ratings
Figure 2. Product Information on Package (Top View)
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
Table 4. Package Branding Information
section of this specification is not implied. Exposure to absolute
Branding Key Field Description
maximum rating conditions for extended periods may affect
345B Part identifier for ADXL345
device reliability.
# RoHS-compliant designation
THERMAL RESISTANCE
yww Date code
vvvv Factory lot code
Table 3. Package Characteristics
CNTY Country of origin
Package Type � � Device Weight
JA JC
14-Terminal LGA 150�C/W 85�C/W 30 mg
ESD CAUTION
Rev. C | Page 6 of 40
07925-102
ADXL345
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADXL345
TOP VIEW
(Not to Scale)
SCL/SCLK
VDD I/O 1 13 SDA/SDI/SDIO
14
2 12 SDO/ALT ADDRESS
GND
3 11 RESERVED
RESERVED
+x
4 10 NC
GND
+y
+z
5 9 INT2
GND
VS 6 7 8 INT1
CS
Figure 3. Pin Configuration (Top View)
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 V Digital Interface Supply Voltage.
DD I/O
2 GND This pin must be connected to ground.
3 RESERVED Reserved. This pin must be connected to V or left open.
S
4 GND This pin must be connected to ground.
5 GND This pin must be connected to ground.
6 V Supply Voltage.
S
7 CS Chip Select.
8 INT1 Interrupt 1 Output.
9 INT2 Interrupt 2 Output.
10 NC Not Internally Connected.
11 RESERVED Reserved. This pin must be connected to ground or left open.
12 SDO/ALT ADDRESS Serial Data Output (SPI 4-Wire)/Alternate I2C Address Select (I2C).
13 SDA/SDI/SDIO Serial Data (I2C)/Serial Data Input (SPI 4-Wire)/Serial Data Input and Output (SPI 3-Wire).
14 SCL/SCLK Serial Communications Clock. SCL is the clock for I2C, and SCLK is the clock for SPI.
Rev. C | Page 7 of 40
07925-002
ADXL345
TYPICAL PERFORMANCE CHARACTERISTICS
20 20
18 18
16 16
14 14
12 12
10 10
8 8
6 6
4 4
2 2
0 0
150 100 50 0 50 100 150 150 100 50 0 50 100 150
ZERO g OFFSET (mg) ZERO g OFFSET (mg)
Figure 4. X-Axis Zero g Offset at 25�C, V = 2.5 V
S Figure 7. X-Axis Zero g Offset at 25�C, V = 3.3 V
S
20 20
18 18
16 16
14 14
12 12
10 10
8 8
6 6
4 4
2 2
0
0
150 100 50 0 50 100 150 150 100 50 0 50 100 150
ZERO g OFFSET (mg) ZERO g OFFSET (mg)
Figure 5. Y-Axis Zero g Offset at 25�C, V = 2.5 V Figure 8. Y-Axis Zero g Offset at 25�C, V = 3.3 V
S S
20
20
18
18
16
16
14
14
12
12
10
10
8
8
6
6
4
4
2
2
0
0
150 100 50 0 50 100 150
150 100 50 0 50 100 150
ZERO g OFFSET (mg)
ZERO g OFFSET (mg)
Figure 6. Z-Axis Zero g Offset at 25�C, V = 2.5 V
S
Figure 9. Z-Axis Zero g Offset at 25�C, V = 3.3 V
S
Rev. C | Page 8 of 40
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PERCENT OF POPULATION (%)
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PERCENT OF POPULATION (%)
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ADXL345
30
150
N = 16
AVDD = DVDD = 2.5V
25 100
20 50
15 0
10 50
5
100
0
150
2.0 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0
40 20 0 20 40 60 80 100
ZERO g OFFSET TEMPERATURE COEFFICIENT (mg/�C)
TEMPERATURE (�C)
Figure 10. X-Axis Zero g Offset Temperature Coefficient, V = 2.5 V
S
Figure 13. X-Axis Zero g Offset vs. Temperature
Eight Parts Soldered to PCB, V = 2.5 V
S
30
150
N = 16
AVDD = DVDD = 2.5V
25
100
20
50
15
0
10
50
5
100
0
150
2.0 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0
40 20 0 20 40 60 80 100
ZERO g OFFSET TEMPERATURE COEFFICIENT (mg/�C)
TEMPERATURE (�C)
Figure 11. Y-Axis Zero g Offset Temperature Coefficient, V = 2.5 V
S
Figure 14. Y-Axis Zero g Offset vs. Temperature
Eight Parts Soldered to PCB, V = 2.5 V
S
25
150
N = 16
AVDD = DVDD = 2.5V
100
20
50
15
0
10
50
5
100
0
150
2.0 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0
40 20 0 20 40 60 80 100
ZERO g OFFSET TEMPERATURE COEFFICIENT (mg/�C)
TEMPERATURE (�C)
Figure 12. Z-Axis Zero g Offset Temperature Coefficient, V = 2.5 V
S Figure 15. Z-Axis Zero g Offset vs. Temperature
Eight Parts Soldered to PCB, V = 2.5 V
S
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)
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)
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)
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ADXL345
55 40
50
35
45
30
40
35
25
30
20
25
15
20
15
10
10
5
5
0
0
0.02 0.01 0 0.01 0.02
230 234 238 242 246 250 254 258 262 266 270 274 278 282
SENSITIVITY TEMPERATURE COEFFICIENT (%/�C)
SENSITIVITY (LSB/g)
Figure 19. X-Axis Sensitivity Temperature Coefficient, V = 2.5 V
Figure 16. X-Axis Sensitivity at 25�C, V = 2.5 V, Full Resolution S
S
40
55
50
35
45
30
40
35 25
30
20
25
15
20
15
10
10
5
5
0
0
0.02 0.01 0 0.01 0.02
230 234 238 242 246 250 254 258 262 266 270 274 278 282
SENSITIVITY TEMPERATURE COEFFICIENT (%/�C)
SENSITIVITY (LSB/g)
Figure 17. Y-Axis Sensitivity at 25�C, V = 2.5 V, Full Resolution Figure 20. Y-Axis Sensitivity Temperature Coefficient, V = 2.5 V
S S
55 40
50
35
45
30
40
35
25
30
20
25
15
20
15
10
10
5
5
0
0
0.02 0.01 0 0.01 0.02
230 234 238 242 246 250 254 258 262 266 270 274 278 282
SENSITIVITY TEMPERATURE COEFFICIENT (%/�C)
SENSITIVITY (LSB/g)
Figure 21. Z-Axis Sensitivity Temperature Coefficient, V = 2.5 V
S
Figure 18. Z-Axis Sensitivity at 25�C, V = 2.5 V, Full Resolution
S
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280 280
275 275
270 270
265 265
260 260
255 255
250 250
245 245
240 240
235 235
230 230
40 20 0 20 40 60 80 100 120 40 20 0 20 40 60 80 100 120
TEMPERATURE (�C) TEMPERATURE (�C)
Figure 22. X-Axis Sensitivity vs. Temperature Figure 25. X-Axis Sensitivity vs. Temperature
Eight Parts Soldered to PCB, V = 2.5 V, Full Resolution Eight Parts Soldered to PCB, V = 3.3 V, Full Resolution
S S
280 280
275 275
270 270
265 265
260 260
255 255
250 250
245 245
240 240
235 235
230 230
40 20 0 20 40 60 80 100 120 40 20 0 20 40 60 80 100 120
TEMPERATURE (�C) TEMPERATURE (�C)
Figure 23. Y-Axis Sensitivity vs. Temperature Figure 26. Y-Axis Sensitivity vs. Temperature
Eight Parts Soldered to PCB, V = 2.5 V, Full Resolution Eight Parts Soldered to PCB, V = 3.3 V, Full Resolution
S S
280 280
275 275
270 270
265 265
260 260
255 255
250 250
245 245
240 240
235 235
230 230
40 20 0 20 40 60 80 100 120 40 20 0 20 40 60 80 100 120
TEMPERATURE (�C) TEMPERATURE (�C)
Figure 24. Z-Axis Sensitivity vs. Temperature Figure 27. Z-Axis Sensitivity vs. Temperature
Eight Parts Soldered to PCB, V = 2.5 V, Full Resolution Eight Parts Soldered to PCB, V = 3.3 V, Full Resolution
S S
Rev. C | Page 11 of 40
SENSITIVITY (LSB/
g
)
SENSITIVITY (LSB/
g
)
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SENSITIVITY (LSB/
g
)
SENSITIVITY (LSB/
g
)
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g
)
SENSITIVITY (LSB/
g
)
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ADXL345
60 25
50
20
40
15
30
10
20
5
10
0
0
0.2 0.5 0.8 1.1 1.4 1.7 2.0
100 110 120 130 140 150 160 170 180 190 200
CURRENT CONSUMPTION (�A)
SELF-TEST RESPONSE (g)
Figure 31. Current Consumption at 25�C, 100 Hz Output Data Rate, V = 2.5 V
Figure 28. X-Axis Self-Test Response at 25�C, V = 2.5 V S
S
160
60
140
50
120
40
100
80
30
60
20
40
10
20
0
0
1.60 3.12 6.25 12.50 25 50 100 200 400 800 1600 3200
0.2 0.5 0.8 1.1 1.4 1.7 2.0
OUTPUT DATA RATE (Hz)
SELF-TEST RESPONSE (g)
Figure 29. Y-Axis Self-Test Response at 25�C, V = 2.5 V
S Figure 32. Current Consumption vs. Output Data Rate at 25�C 10 Parts,
V = 2.5 V
S
60 200
50
150
40
30 100
20
50
10
0 0
2.02.42.83.23.6
0.3 0.9 1.5 2.1 2.7 3.3
SELF-TEST RESPONSE (g)
SUPPLY VOLTAGE (V)
Figure 30. Z-Axis Self-Test Response at 25�C, V = 2.5 V Figure 33. Supply Current vs. Supply Voltage, V at 25�C
S S
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ADXL345
THEORY OF OPERATION
The ADXL345 is a complete 3-axis acceleration measurement
POWER SEQUENCING
system with a selectable measurement range of ą2 g, ą4 g, ą8 g,
Power can be applied to V or V in any sequence without
S DD I/O
or ą16 g. It measures both dynamic acceleration resulting from
damaging the ADXL345. All possible power-on modes are
motion or shock and static acceleration, such as gravity, that
summarized in Table 6. The interface voltage level is set with
allows the device to be used as a tilt sensor.
the interface supply voltage, V , which must be present to
DD I/O
The sensor is a polysilicon surface-micromachined structure ensure that the ADXL345 does not create a conflict on the
built on top of a silicon wafer. Polysilicon springs suspend the communication bus. For single-supply operation, V can be
DD I/O
structure over the surface of the wafer and provide a resistance the same as the main supply, V . In a dual-supply application,
S
against forces due to applied acceleration. however, V can differ from V to accommodate the desired
DD I/O S
interface voltage, as long as V is greater than or equal to V .
S DD I/O
Deflection of the structure is measured using differential capacitors
that consist of independent fixed plates and plates attached to the After V is applied, the device enters standby mode, where power
S
moving mass. Acceleration deflects the proof mass and unbalances consumption is minimized and the device waits for V to be
DD I/O
the differential capacitor, resulting in a sensor output whose ampli- applied and for the command to enter measurement mode to be
tude is proportional to acceleration. Phase-sensitive demodulation received. (This command can be initiated by setting the measure
is used to determine the magnitude and polarity of the acceleration.
bit (Bit D3) in the POWER_CTL register (Address 0x2D).) In
addition, while the device is in standby mode, any register can be
written to or read from to configure the part. It is recommended
to configure the device in standby mode and then to enable
measurement mode. Clearing the measure bit returns the
device to the standby mode.
Table 6. Power Sequencing
Condition V V Description
S DD I/O
Power Off Off Off The device is completely off, but there is a potential for a communication bus conflict.
Bus Disabled On Off The device is on in standby mode, but communication is unavailable and creates a conflict on
the communication bus. The duration of this state should be minimized during power-up to
prevent a conflict.
Bus Enabled Off On No functions are available, but the device does not create a conflict on the communication bus.
Standby or Measurement On On At power-up, the device is in standby mode, awaiting a command to enter measurement
mode, and all sensor functions are off. After the device is instructed to enter measurement
mode, all sensor functions are available.
Rev. C | Page 13 of 40
ADXL345
POWER SAVINGS
Table 8. Typical Current Consumption vs. Data Rate,
Power Modes
Low Power Mode (T = 25�C, V = 2.5 V, V = 1.8 V)
A S DD I/O
Output Data
The ADXL345 automatically modulates its power consumption
Rate (Hz) Bandwidth (Hz) Rate Code I (�A)
DD
in proportion to its output data rate, as outlined in Table 7. If
400 200 1100 90
additional power savings is desired, a lower power mode is
200 100 1011 60
available. In this mode, the internal sampling rate is reduced,
100 50 1010 50
allowing for power savings in the 12.5 Hz to 400 Hz data rate
50 25 1001 45
range at the expense of slightly greater noise. To enter low power
25 12.5 1000 40
mode, set the LOW_POWER bit (Bit 4) in the BW_RATE register
12.5 6.25 0111 34
(Address 0x2C). The current consumption in low power mode
is shown in Table 8 for cases where there is an advantage to
Auto Sleep Mode
using low power mode. Use of low power mode for a data rate
Additional power can be saved if the ADXL345 automatically
not shown in Table 8 does not provide any advantage over the same
switches to sleep mode during periods of inactivity. To enable
data rate in normal power mode. Therefore, it is recommended
this feature, set the THRESH_INACT register (Address 0x25)
that only data rates shown in Table 8 are used in low power mode.
and the TIME_INACT register (Address 0x26) each to a value
The current consumption values shown in Table 7 and Table 8
that signifies inactivity (the appropriate value depends on the
are for a V of 2.5 V.
S
application), and then set the AUTO_SLEEP bit (Bit D4) and the
Table 7. Typical Current Consumption vs. Data Rate
link bit (Bit D5) in the POWER_CTL register (Address 0x2D).
(T = 25�C, V = 2.5 V, V = 1.8 V) Current consumption at the sub-12.5 Hz data rates that are
A S DD I/O
used in this mode is typically 23 �A for a V of 2.5 V.
S
Output Data
Rate (Hz) Bandwidth (Hz) Rate Code I (�A)
DD
Standby Mode
3200 1600 1111 140
For even lower power operation, standby mode can be used. In
1600 800 1110 90
standby mode, current consumption is reduced to 0.1 �A (typical).
800 400 1101 140
In this mode, no measurements are made. Standby mode is
400 200 1100 140
entered by clearing the measure bit (Bit D3) in the POWER_CTL
200 100 1011 140
register (Address 0x2D). Placing the device into standby mode
100 50 1010 140
preserves the contents of FIFO.
50 25 1001 90
25 12.5 1000 60
12.5 6.25 0111 50
6.25 3.13 0110 45
3.13 1.56 0101 40
1.56 0.78 0100 34
0.78 0.39 0011 23
0.39 0.20 0010 23
0.20 0.10 0001 23
0.10 0.05 0000 23
Rev. C | Page 14 of 40
ADXL345
SERIAL COMMUNICATIONS
I2C and SPI digital communications are available. In both cases, To read or write multiple bytes in a single transmission, the
CS W
the ADXL345 operates as a slave. I2C mode is enabled if the multiple-byte bit, located after the R/ bit in the first byte transfer
CS (MB in Figure 37 to Figure 39), must be set. After the register
pin is tied high to V . The pin should always be tied high
DD I/O
addressing and the first byte of data, each subsequent set of
to V or be driven by an external controller because there is
DD I/O
clock pulses (eight clock pulses) causes the ADXL345 to point
CS
no default mode if the pin is left unconnected. Therefore, not
to the next register for a read or write. This shifting continues
taking these precautions may result in an inability to communicate
CS
until the clock pulses cease and is deasserted. To perform reads or
CS
with the part. In SPI mode, the pin is controlled by the bus
CS
writes on different, nonsequential registers, must be deasserted
master. In both SPI and I2C modes of operation, data transmitted
between transmissions and the new register must be addressed
from the ADXL345 to the master device should be ignored
separately.
during writes to the ADXL345.
The timing diagram for 3-wire SPI reads or writes is shown
SPI
in Figure 39. The 4-wire equivalents for SPI writes and reads
For SPI, either 3- or 4-wire configuration is possible, as shown in
are shown in Figure 37 and Figure 38, respectively. For correct
the connection diagrams in Figure 34 and Figure 35. Clearing the
operation of the part, the logic thresholds and timing parameters
SPI bit (Bit D6) in the DATA_FORMAT register (Address 0x31)
in Table 9 and Table 10 must be met at all times.
selects 4-wire mode, whereas setting the SPI bit selects 3-wire
Use of the 3200 Hz and 1600 Hz output data rates is only
mode. The maximum SPI clock speed is 5 MHz with 100 pF
recommended with SPI communication rates greater than or
maximum loading, and the timing scheme follows clock polarity
equal to 2 MHz. The 800 Hz output data rate is recommended
(CPOL) = 1 and clock phase (CPHA) = 1. If power is applied to
only for communication speeds greater than or equal to 400 kHz,
the ADXL345 before the clock polarity and phase of the host
and the remaining data rates scale proportionally. For example,
CS
processor are configured, the pin should be brought high
the minimum recommended communication speed for a 200 Hz
before changing the clock polarity and phase. When using 3-wire
output data rate is 100 kHz. Operation at an output data rate
SPI, it is recommended that the SDO pin be either pulled up to
above the recommended maximum may result in undesirable
V or pulled down to GND via a 10 k� resistor.
DD I/O
effects on the acceleration data, including missing samples or
additional noise.
ADXL345 PROCESSOR
Preventing Bus Traffic Errors
CS D OUT
CS
The ADXL346 pin is used both for initiating SPI
SDIO D IN/OUT
transactions, and for enabling I2C mode. When the ADXL346 is
SDO
CS
used on a SPI bus with multiple devices, its pin is held high
SCLK D OUT
while the master communicates with the other devices. There
Figure 34. 3-Wire SPI Connection Diagram
may be conditions where a SPI command transmitted to
another device looks like a valid I2C command. In this case, the
ADXL345 PROCESSOR
ADXL346 would interpret this as an attempt to communicate in
CS D OUT
SDI D OUT I2C mode, and could interfere with other bus traffic. Unless bus
SDO D IN
traffic can be adequately controlled to assure such a condition
SCLK D OUT
never occurs, it is recommended to add a logic gate in front of
the SDI pin as shown in Figure 36. This OR gate will hold the
Figure 35. 4-Wire SPI Connection Diagram
CS
SDA line high when is high to prevent SPI bus traffic at the
CS
is the serial port enable line and is controlled by the SPI
ADXL346 from appearing as an I2C start command.
master. This line must go low at the start of a transmission and
high at the end of a transmission, as shown in Figure 37. SCLK ADXL345 PROCESSOR
is the serial port clock and is supplied by the SPI master. SCLK
CS D OUT
SDIO D IN/OUT
should idle high during a period of no transmission. SDI and
SDO
SDO are the serial data input and output, respectively. Data is
SCLK D OUT
updated on the falling edge of SCLK and should be sampled on
the rising edge of SCLK.
Figure 36. Recommended SPI Connection Diagram when Using Multiple SPI
Devices on a Single Bus
Rev. C | Page 15 of 40
07925-004
07925-003
07925-104
ADXL345
CS
tSCLK tM tS
tQUIET tCS,DIS
tDELAY
SCLK
tHOLD
tSETUP
W MB A5 A0 D7 D0
SDI
tSDO
tDIS
ADDRESS BITS DATA BITS
SDO XX X XX X
Figure 37. SPI 4-Wire Write
CS
tSCLK tM tS
tQUIET tCS,DIS
tDELAY
SCLK
tHOLD
tSETUP
RMB A5 A0 X X
SDI
tSDO ADDRESS BITS
tDIS
SDO XX X X D7 D0
DATA BITS
Figure 38. SPI 4-Wire Read
CS
tDELAY
tSCLK tM tS
tQUIET tCS,DIS
SCLK
tSETUP tSDO
tHOLD
R/W MB A5 A0 D7 D0
SDIO
ADDRESS BITS DATA BITS
SDO
NOTES
1. tSDO IS ONLY PRESENT DURING READS.
Figure 39. SPI 3-Wire Read/Write
Rev. C | Page 16 of 40
07925-017
07925-018
07925-019
ADXL345
Table 9. SPI Digital Input/Output
Limit1
Parameter Test Conditions Min Max Unit
Digital Input
Low Level Input Voltage (V ) 0.3 � V V
IL DD I/O
High Level Input Voltage (V ) 0.7 � V V
IH DD I/O
Low Level Input Current (I ) V = V 0.1 �A
IL IN DD I/O
High Level Input Current (I ) V = 0 V -0.1 �A
IH IN
Digital Output
Low Level Output Voltage (V ) I = 10 mA 0.2 � V V
OL OL DD I/O
High Level Output Voltage (V ) I = -4 mA 0.8 � V V
OH OH DD I/O
Low Level Output Current (I ) V = V 10 mA
OL OL OL, max
High Level Output Current (I ) V = V -4 mA
OH OH OH, min
Pin Capacitance f = 1 MHz, V = 2.5 V 8 pF
IN IN
1
Limits based on characterization results, not production tested.
Table 10. SPI Timing (T = 25�C, V = 2.5 V, V = 1.8 V)1
A S DD I/O
Limit2, 3
Parameter Min Max Unit Description
f 5 MHz SPI clock frequency
SCLK
t 200 ns 1/(SPI clock frequency) mark-space ratio for the SCLK input is 40/60 to 60/40
SCLK
t 5 ns CS falling edge to SCLK falling edge
DELAY
t 5 ns SCLK rising edge to CS rising edge
QUIET
t 10 ns CS rising edge to SDO disabled
DIS
t 150 ns CS deassertion between SPI communications
CS,DIS
t 0.3 � t ns SCLK low pulse width (space)
S SCLK
t 0.3 � t ns SCLK high pulse width (mark)
M SCLK
t 5 ns SDI valid before SCLK rising edge
SETUP
t 5 ns SDI valid after SCLK rising edge
HOLD
t 40 ns SCLK falling edge to SDO/SDIO output transition
SDO
4
t 20 ns SDO/SDIO output high to output low transition
R
4
t 20 ns SDO/SDIO output low to output high transition
F
1
CS
The , SCLK, SDI, and SDO pins are not internally pulled up or down; they must be driven for proper operation.
2
Limits based on characterization results, characterized with f = 5 MHz and bus load capacitance of 100 pF; not production tested.
SCLK
3
The timing values are measured corresponding to the input thresholds (V and V ) given in Table 9.
IL IH
4
Output rise and fall times measured with capacitive load of 150 pF.
Rev. C | Page 17 of 40
ADXL345
Due to communication speed limitations, the maximum output
I2C
data rate when using 400 kHz I2C is 800 Hz and scales linearly
CS
With tied high to V , the ADXL345 is in I2C mode,
DD I/O
with a change in the I2C communication speed. For example,
requiring a simple 2-wire connection, as shown in Figure 40.
using I2C at 100 kHz would limit the maximum ODR to 200 Hz.
The ADXL345 conforms to the UM10204 I2C-Bus Specification
Operation at an output data rate above the recommended maxi-
and User Manual, Rev. 03 19 June 2007, available from NXP
mum may result in undesirable effect on the acceleration data,
Semiconductor. It supports standard (100 kHz) and fast (400 kHz)
including missing samples or additional noise.
data transfer modes if the bus parameters given in Table 11
VDD I/O
and Table 12 are met. Single- or multiple-byte reads/writes are
supported, as shown in Figure 41. With the ALT ADDRESS pin
high, the 7-bit I2C address for the device is 0x1D, followed by RP RP PROCESSOR
ADXL345
W
the R/ bit. This translates to 0x3A for a write and 0x3B for a
CS
W
read. An alternate I2C address of 0x53 (followed by the R/ bit) SDA D IN/OUT
ALT ADDRESS
can be chosen by grounding the ALT ADDRESS pin (Pin 12).
SCL D OUT
This translates to 0xA6 for a write and 0xA7 for a read.
There are no internal pull-up or pull-down resistors for any
Figure 40. I2C Connection Diagram (Address 0x53)
unused pins; therefore, there is no known state or default state
CS
for the or ALT ADDRESS pin if left floating or unconnected. If other devices are connected to the same I2C bus, the nominal
operating voltage level of these other devices cannot exceed V
CS DD I/O
It is required that the pin be connected to V and that
DD I/O
by more than 0.3 V. External pull-up resistors, R , are necessary for
P
the ALT ADDRESS pin be connected to either V or GND
DD I/O
proper I2C operation. Refer to the UM10204 I2C-Bus Specification
when using I2C.
and User Manual, Rev. 03 19 June 2007, when selecting pull-up
resistor values to ensure proper operation.
Table 11. I2C Digital Input/Output
Limit1
Parameter Test Conditions Min Max Unit
Digital Input
Low Level Input Voltage (V ) 0.3 � V V
IL DD I/O
High Level Input Voltage (V ) 0.7 � V V
IH DD I/O
Low Level Input Current (I ) V = V 0.1 �A
IL IN DD I/O
High Level Input Current (I ) V = 0 V -0.1 �A
IH IN
Digital Output
Low Level Output Voltage (V ) V < 2 V, I = 3 mA 0.2 � V V
OL DD I/O OL DD I/O
V e" 2 V, I = 3 mA 400 mV
DD I/O OL
Low Level Output Current (I ) V = V 3 mA
OL OL OL, max
Pin Capacitance f = 1 MHz, V = 2.5 V 8 pF
IN IN
1
Limits based on characterization results; not production tested.
SINGLE-BYTE WRITE
MASTER START SLAVE ADDRESS + WRITE REGISTER ADDRESS DATA STOP
SLAVE ACK ACK ACK
MULTIPLE-BYTE WRITE
MASTER START SLAVE ADDRESS + WRITE REGISTER ADDRESS DATA DATA STOP
SLAVE ACK ACK ACK ACK
SINGLE-BYTE READ
MASTER START SLAVE ADDRESS + WRITE REGISTER ADDRESS START1 SLAVE ADDRESS + READ NACK STOP
SLAVE ACK ACK ACK DATA
MULTIPLE-BYTE READ
MASTER START SLAVE ADDRESS + WRITE REGISTER ADDRESS START1 SLAVE ADDRESS + READ ACK NACK STOP
SLAVE ACK ACK ACK DATA DATA
NOTES
1. THIS START IS EITHER A RESTART OR A STOP FOLLOWED BY A START.
2. THE SHADED AREAS REPRESENT WHEN THE DEVICE IS LISTENING.
Figure 41. I2C Device Addressing
Rev. C | Page 18 of 40
07925-008
07925-033
ADXL345
Table 12. I2C Timing (T = 25�C, V = 2.5 V, V = 1.8 V)
A S DD I/O
Limit1, 2
Parameter Min Max Unit Description
f 400 kHz SCL clock frequency
SCL
t 2.5 �s SCL cycle time
1
t 0.6 �s t , SCL high time
2 HIGH
t 1.3 �s t , SCL low time
3 LOW
t 0.6 �s t , start/repeated start condition hold time
4 HD, STA
t 100 ns t , data setup time
5 SU, DAT
3 , 4 , 5, 6
t 0 0.9 �s t , data hold time
6 HD, DAT
t 0.6 �s t , setup time for repeated start
7 SU, STA
t 0.6 �s t , stop condition setup time
8 SU, STO
t 1.3 �s t , bus-free time between a stop condition and a start condition
9 BUF
t 300 ns t , rise time of both SCL and SDA when receiving
10 R
0 ns t , rise time of both SCL and SDA when receiving or transmitting
R
t 300 ns t , fall time of SDA when receiving
11 F
250 ns t , fall time of both SCL and SDA when transmitting
F
C 400 pF Capacitive load for each bus line
b
1
Limits based on characterization results, with f = 400 kHz and a 3 mA sink current; not production tested.
SCL
2
All values referred to the V and the V levels given in Table 11.
IH IL
3
t is the data hold time that is measured from the falling edge of SCL. It applies to data in transmission and acknowledge.
6
4
A transmitting device must internally provide an output hold time of at least 300 ns for the SDA signal (with respect to V of the SCL signal) to bridge the
IH(min)
undefined region of the falling edge of SCL.
5
The maximum t value must be met only if the device does not stretch the low period (t ) of the SCL signal.
6 3
6
The maximum value for t is a function of the clock low time (t ), the clock rise time (t ), and the minimum data setup time (t ). This value is calculated as
6 3 10 5(min)
t = t - t - t .
6(max) 3 10 5(min)
SDA
t3 t4
t9
t10 t11
SCL
t2 t7 t1 t8
t4 t6 t5
START REPEATED STOP
CONDITION START CONDITION
CONDITION
Figure 42. I2C Timing Diagram
Rev. C | Page 19 of 40
07925-034
ADXL345
DOUBLE_TAP
INTERRUPTS
The DOUBLE_TAP bit is set when two acceleration events
The ADXL345 provides two output pins for driving interrupts:
that are greater than the value in the THRESH_TAP register
INT1 and INT2. Both interrupt pins are push-pull, low impedance
(Address 0x1D) occur for less time than is specified in the DUR
pins with output specifications shown in Table 13. The default
register (Address 0x21), with the second tap starting after the
configuration of the interrupt pins is active high. This can be
time specified by the latent register (Address 0x22) but within
changed to active low by setting the INT_INVERT bit in the
the time specified in the window register (Address 0x23). See
DATA_FORMAT (Address 0x31) register. All functions can
the Tap Detection section for more details.
be used simultaneously, with the only limiting feature being
Activity
that some functions may need to share interrupt pins.
The activity bit is set when acceleration greater than the value stored
Interrupts are enabled by setting the appropriate bit in the
in the THRESH_ACT register (Address 0x24) is experienced on
INT_ENABLE register (Address 0x2E) and are mapped to
any participating axis, set by the ACT_INACT_CTL register
either the INT1 pin or the INT2 pin based on the contents
(Address 0x27).
of the INT_MAP register (Address 0x2F). When initially
Inactivity
configuring the interrupt pins, it is recommended that the
The inactivity bit is set when acceleration of less than the
functions and interrupt mapping be done before enabling the
value stored in the THRESH_INACT register (Address 0x25) is
interrupts. When changing the configuration of an interrupt, it
experienced for more time than is specified in the TIME_INACT
is recommended that the interrupt be disabled first, by clearing
register (Address 0x26) on all participating axes, as set by the
the bit corresponding to that function in the INT_ENABLE
ACT_INACT_CTL register (Address 0x27). The maximum value
register, and then the function be reconfigured before enabling
for TIME_INACT is 255 sec.
the interrupt again. Configuration of the functions while the
interrupts are disabled helps to prevent the accidental generation FREE_FALL
of an interrupt before desired.
The FREE_FALL bit is set when acceleration of less than the
value stored in the THRESH_FF register (Address 0x28) is
The interrupt functions are latched and cleared by either reading the
experienced for more time than is specified in the TIME_FF
data registers (Address 0x32 to Address 0x37) until the interrupt
register (Address 0x29) on all axes (logical AND). The FREE_FALL
condition is no longer valid for the data-related interrupts or by
interrupt differs from the inactivity interrupt as follows: all axes
reading the INT_SOURCE register (Address 0x30) for the
always participate and are logically AND ed, the timer period is
remaining interrupts. This section describes the interrupts
much smaller (1.28 sec maximum), and the mode of operation is
that can be set in the INT_ENABLE register and monitored
always dc-coupled.
in the INT_SOURCE register.
Watermark
DATA_READY
The watermark bit is set when the number of samples in FIFO
The DATA_READY bit is set when new data is available and is
equals the value stored in the samples bits (Register FIFO_CTL,
cleared when no new data is available.
Address 0x38). The watermark bit is cleared automatically when
SINGLE_TAP
FIFO is read, and the content returns to a value below the value
The SINGLE_TAP bit is set when a single acceleration event
stored in the samples bits.
that is greater than the value in the THRESH_TAP register
(Address 0x1D) occurs for less time than is specified in the
DUR register (Address 0x21).
Table 13. Interrupt Pin Digital Output
Limit1
Parameter Test Conditions Min Max Unit
Digital Output
Low Level Output Voltage (V ) I = 300 �A 0.2 � V V
OL OL DD I/O
High Level Output Voltage (V ) I = -150 �A 0.8 � V V
OH OH DD I/O
Low Level Output Current (I ) V = V 300 �A
OL OL OL, max
High Level Output Current (I ) V = V -150 �A
OH OH OH, min
Pin Capacitance f = 1 MHz, V = 2.5 V 8 pF
IN IN
Rise/Fall Time
Rise Time (t )2 C = 150 pF 210 ns
R LOAD
Fall Time (t )3 C = 150 pF 150 ns
F LOAD
1
Limits based on characterization results, not production tested.
2
Rise time is measured as the transition time from V to V of the interrupt pin.
OL, max OH, min
3
Fall time is measured as the transition time from V to V of the interrupt pin.
OH, min OL, max
Rev. C | Page 20 of 40
ADXL345
Overrun Trigger Mode
The overrun bit is set when new data replaces unread data. The In trigger mode, FIFO accumulates samples, holding the latest
precise operation of the overrun function depends on the FIFO 32 samples from measurements of the x-, y-, and z-axes. After
mode. In bypass mode, the overrun bit is set when new data replaces a trigger event occurs and an interrupt is sent to the INT1 or
unread data in the DATAX, DATAY, and DATAZ registers (Address INT2 pin (determined by the trigger bit in the FIFO_CTL register),
0x32 to Address 0x37). In all other modes, the overrun bit is set FIFO keeps the last n samples (where n is the value specified by
when FIFO is filled. The overrun bit is automatically cleared when the samples bits in the FIFO_CTL register) and then operates in
the contents of FIFO are read. FIFO mode, collecting new samples only when FIFO is not full.
A delay of at least 5 �s should be present between the trigger event
FIFO
occurring and the start of reading data from the FIFO to allow
The ADXL345 contains patent pending technology for an
the FIFO to discard and retain the necessary samples. Additional
embedded memory management system with 32-level FIFO
trigger events cannot be recognized until the trigger mode is
that can be used to minimize host processor burden. This buffer
reset. To reset the trigger mode, set the device to bypass mode
has four modes: bypass, FIFO, stream, and trigger (see FIFO
and then set the device back to trigger mode. Note that the FIFO
Modes). Each mode is selected by the settings of the
data should be read first because placing the device into bypass
FIFO_MODE bits (Bits[D7:D6]) in the FIFO_CTL register
mode clears FIFO.
(Address 0x38).
Retrieving Data from FIFO
Bypass Mode
The FIFO data is read through the DATAX, DATAY, and DATAZ
In bypass mode, FIFO is not operational and, therefore,
registers (Address 0x32 to Address 0x37). When the FIFO is in
remains empty.
FIFO, stream, or trigger mode, reads to the DATAX, DATAY,
FIFO Mode and DATAZ registers read data stored in the FIFO. Each time
data is read from the FIFO, the oldest x-, y-, and z-axes data are
In FIFO mode, data from measurements of the x-, y-, and z-axes
placed into the DATAX, DATAY and DATAZ registers.
are stored in FIFO. When the number of samples in FIFO equals
the level specified in the samples bits of the FIFO_CTL register If a single-byte read operation is performed, the remaining
(Address 0x38), the watermark interrupt is set. FIFO continues bytes of data for the current FIFO sample are lost. Therefore, all
accumulating samples until it is full (32 samples from measurements axes of interest should be read in a burst (or multiple-byte) read
of the x-, y-, and z-axes) and then stops collecting data. After FIFO operation. To ensure that the FIFO has completely popped (that
stops collecting data, the device continues to operate; therefore, is, that new data has completely moved into the DATAX, DATAY,
features such as tap detection can be used after FIFO is full. The and DATAZ registers), there must be at least 5 �s between the
watermark interrupt continues to occur until the number of end of reading the data registers and the start of a new read of
samples in FIFO is less than the value stored in the samples bits the FIFO or a read of the FIFO_STATUS register (Address 0x39).
of the FIFO_CTL register. The end of reading a data register is signified by the transition
CS
from Register 0x37 to Register 0x38 or by the pin going high.
Stream Mode
For SPI operation at 1.6 MHz or less, the register addressing
In stream mode, data from measurements of the x-, y-, and z-
portion of the transmission is a sufficient delay to ensure that
axes are stored in FIFO. When the number of samples in FIFO
the FIFO has completely popped. For SPI operation greater than
equals the level specified in the samples bits of the FIFO_CTL
CS
1.6 MHz, it is necessary to deassert the pin to ensure a total
register (Address 0x38), the watermark interrupt is set. FIFO
delay of 5 �s; otherwise, the delay is not sufficient. The total delay
continues accumulating samples and holds the latest 32 samples
necessary for 5 MHz operation is at most 3.4 �s. This is not a
from measurements of the x-, y-, and z-axes, discarding older
concern when using I2C mode because the communication rate is
data as new data arrives. The watermark interrupt continues
low enough to ensure a sufficient delay between FIFO reads.
occurring until the number of samples in FIFO is less than the
value stored in the samples bits of the FIFO_CTL register.
Rev. C | Page 21 of 40
ADXL345
SELF-TEST
Table 14. Self-Test Output Scale Factors for Different Supply
Voltages, V
S
The ADXL345 incorporates a self-test feature that effectively
Supply Voltage, V (V) X-Axis, Y-Axis Z-Axis
S
tests its mechanical and electronic systems simultaneously.
2.00 0.64 0.8
When the self-test function is enabled (via the SELF_TEST bit
2.50 1.00 1.00
in the DATA_FORMAT register, Address 0x31), an electrostatic
3.30 1.77 1.47
force is exerted on the mechanical sensor. This electrostatic force
3.60 2.11 1.69
moves the mechanical sensing element in the same manner as
acceleration, and it is additive to the acceleration experienced
Table 15. Self-Test Output in LSB for ą2 g, 10-Bit or Full
by the device. This added electrostatic force results in an output
Resolution (T = 25�C, V = 2.5 V, V = 1.8 V)
A S DD I/O
change in the x-, y-, and z-axes. Because the electrostatic force
2 Axis Min Max Unit
is proportional to V , the output change varies with V . This
S S
X 50 540 LSB
effect is shown in Figure 43. The scale factors shown in Table 14
Y -540 -540 LSB
can be used to adjust the expected self-test output limits for
Z 75 875 LSB
different supply voltages, V . The self-test feature of the ADXL345
S
also exhibits a bimodal behavior. However, the limits shown in
Table 16. Self-Test Output in LSB for ą4 g, 10-Bit Resolution
Table 1 and Table 15 to Table 18 are valid for both potential self-
(T = 25�C, V = 2.5 V, V = 1.8 V)
A S DD I/O
test values due to bimodality. Use of the self-test feature at data
Axis Min Max Unit
rates less than 100 Hz or at 1600 Hz may yield values outside
X 25 270 LSB
these limits. Therefore, the part must be in normal power operation
Y -270 -25 LSB
(LOW_POWER bit = 0 in BW_RATE register, Address 0x2C)
Z 38 438 LSB
and be placed into a data rate of 100 Hz through 800 Hz or 3200 Hz
for the self-test function to operate correctly.
Table 17. Self-Test Output in LSB for ą8 g, 10-Bit Resolution
6
(T = 25�C, V = 2.5 V, V = 1.8 V)
A S DD I/O
Axis Min Max Unit
4
X 12 135 LSB
Y -135 -12 LSB
2
Z 19 219 LSB
0
Table 18. Self-Test Output in LSB for ą16 g, 10-Bit Resolution
(T = 25�C, V = 2.5 V, V = 1.8 V)
A S DD I/O
2
Axis Min Max Unit
X HIGH
X LOW
X 6 67 LSB
Y HIGH
4
Y LOW Y -67 -6 LSB
Z HIGH
Z 10 110 LSB
Z LOW
6
2.0 2.5 3.3 3.6
VS (V)
Figure 43. Self-Test Output Change Limits vs. Supply Voltage
Rev. C | Page 22 of 40
SELF-TEST SHIFT LIMIT (
g
)
07925-242
ADXL345
REGISTER MAP
Table 19.
Address
Hex Dec Name Type Reset Value Description
0x00 0 DEVID R 11100101 Device ID
0x01 to 0x1C 1 to 28 Reserved Reserved; do not access
0x1D 29 THRESH_TAP R/W 00000000 Tap threshold
0x1E 30 OFSX R/W 00000000 X-axis offset
0x1F 31 OFSY R/W 00000000 Y-axis offset
0x20 32 OFSZ R/W 00000000 Z-axis offset
0x21 33 DUR R/W 00000000 Tap duration
0x22 34 Latent R/W 00000000 Tap latency
0x23 35 Window R/W 00000000 Tap window
0x24 36 THRESH_ACT R/W 00000000 Activity threshold
0x25 37 THRESH_INACT R/W 00000000 Inactivity threshold
0x26 38 TIME_INACT R/W 00000000 Inactivity time
0x27 39 ACT_INACT_CTL R/W 00000000 Axis enable control for activity and inactivity detection
0x28 40 THRESH_FF R/W 00000000 Free-fall threshold
0x29 41 TIME_FF R/W 00000000 Free-fall time
0x2A 42 TAP_AXES R/W 00000000 Axis control for single tap/double tap
0x2B 43 ACT_TAP_STATUS R 00000000 Source of single tap/double tap
0x2C 44 BW_RATE R/W 00001010 Data rate and power mode control
0x2D 45 POWER_CTL R/W 00000000 Power-saving features control
0x2E 46 INT_ENABLE R/W 00000000 Interrupt enable control
0x2F 47 INT_MAP R/W 00000000 Interrupt mapping control
0x30 48 INT_SOURCE R 00000010 Source of interrupts
0x31 49 DATA_FORMAT R/W 00000000 Data format control
0x32 50 DATAX0 R 00000000 X-Axis Data 0
0x33 51 DATAX1 R 00000000 X-Axis Data 1
0x34 52 DATAY0 R 00000000 Y-Axis Data 0
0x35 53 DATAY1 R 00000000 Y-Axis Data 1
0x36 54 DATAZ0 R 00000000 Z-Axis Data 0
0x37 55 DATAZ1 R 00000000 Z-Axis Data 1
0x38 56 FIFO_CTL R/W 00000000 FIFO control
0x39 57 FIFO_STATUS R 00000000 FIFO status
Rev. C | Page 23 of 40
ADXL345
Register 0x25 THRESH_INACT (Read/Write)
REGISTER DEFINITIONS
Register 0x00 DEVID (Read Only) The THRESH_INACT register is eight bits and holds the threshold
D7 D6 D5 D4 D3 D2 D1 D0 value for detecting inactivity. The data format is unsigned, so
the magnitude of the inactivity event is compared with the value
1 1 1 0 0 1 0 1
in the THRESH_INACT register. The scale factor is 62.5 mg/LSB.
The DEVID register holds a fixed device ID code of 0xE5 (345 octal).
A value of 0 may result in undesirable behavior if the inactivity
Register 0x1D THRESH_TAP (Read/Write)
interrupt is enabled.
The THRESH_TAP register is eight bits and holds the threshold
Register 0x26 TIME_INACT (Read/Write)
value for tap interrupts. The data format is unsigned, therefore,
The TIME_INACT register is eight bits and contains an unsigned
the magnitude of the tap event is compared with the value
time value representing the amount of time that acceleration
in THRESH_TAP for normal tap detection. The scale factor is
must be less than the value in the THRESH_INACT register for
62.5 mg/LSB (that is, 0xFF = 16 g). A value of 0 may result in
inactivity to be declared. The scale factor is 1 sec/LSB. Unlike
undesirable behavior if single tap/double tap interrupts are
the other interrupt functions, which use unfiltered data (see the
enabled.
Threshold section), the inactivity function uses filtered output
Register 0x1E, Register 0x1F, Register 0x20 OFSX,
data. At least one output sample must be generated for the
OFSY, OFSZ (Read/Write)
inactivity interrupt to be triggered. This results in the function
The OFSX, OFSY, and OFSZ registers are each eight bits and appearing unresponsive if the TIME_INACT register is set to a
offer user-set offset adjustments in twos complement format value less than the time constant of the output data rate. A value
with a scale factor of 15.6 mg/LSB (that is, 0x7F = 2 g). The of 0 results in an interrupt when the output data is less than the
value stored in the offset registers is automatically added to the value in the THRESH_INACT register.
acceleration data, and the resulting value is stored in the output
Register 0x27 ACT_INACT_CTL (Read/Write)
data registers. For additional information regarding offset
D7 D6 D5 D4
calibration and the use of the offset registers, refer to the Offset
ACT ac/dc ACT_X enable ACT_Y enable ACT_Z enable
Calibration section.
D3 D2 D1 D0
INACT ac/dc INACT_X enable INACT_Y enable INACT_Z enable
Register 0x21 DUR (Read/Write)
The DUR register is eight bits and contains an unsigned time
ACT AC/DC and INACT AC/DC Bits
value representing the maximum time that an event must be
A setting of 0 selects dc-coupled operation, and a setting of 1
above the THRESH_TAP threshold to qualify as a tap event. The
enables ac-coupled operation. In dc-coupled operation, the
scale factor is 625 �s/LSB. A value of 0 disables the single tap/
current acceleration magnitude is compared directly with
double tap functions.
THRESH_ACT and THRESH_INACT to determine whether
Register 0x22 Latent (Read/Write)
activity or inactivity is detected.
The latent register is eight bits and contains an unsigned time
In ac-coupled operation for activity detection, the acceleration
value representing the wait time from the detection of a tap
value at the start of activity detection is taken as a reference
event to the start of the time window (defined by the window
value. New samples of acceleration are then compared to this
register) during which a possible second tap event can be detected.
reference value, and if the magnitude of the difference exceeds
The scale factor is 1.25 ms/LSB. A value of 0 disables the double tap
the THRESH_ACT value, the device triggers an activity interrupt.
function.
Similarly, in ac-coupled operation for inactivity detection, a
Register 0x23 Window (Read/Write)
reference value is used for comparison and is updated whenever
The window register is eight bits and contains an unsigned time the device exceeds the inactivity threshold. After the reference
value representing the amount of time after the expiration of the value is selected, the device compares the magnitude of the
latency time (determined by the latent register) during which a difference between the reference value and the current acceleration
second valid tap can begin. The scale factor is 1.25 ms/LSB. A with THRESH_INACT. If the difference is less than the value in
value of 0 disables the double tap function. THRESH_INACT for the time in TIME_INACT, the device is
considered inactive and the inactivity interrupt is triggered.
Register 0x24 THRESH_ACT (Read/Write)
The THRESH_ACT register is eight bits and holds the threshold
value for detecting activity. The data format is unsigned, so the
magnitude of the activity event is compared with the value in
the THRESH_ACT register. The scale factor is 62.5 mg/LSB.
A value of 0 may result in undesirable behavior if the activity
interrupt is enabled.
Rev. C | Page 24 of 40
ADXL345
ACT_x Enable Bits and INACT_x Enable Bits Asleep Bit
A setting of 1 enables x-, y-, or z-axis participation in detecting A setting of 1 in the asleep bit indicates that the part is asleep,
activity or inactivity. A setting of 0 excludes the selected axis from and a setting of 0 indicates that the part is not asleep. This bit
participation. If all axes are excluded, the function is disabled. toggles only if the device is configured for auto sleep. See the
For activity detection, all participating axes are logically OR ed, AUTO_SLEEP Bit section for more information on autosleep
causing the activity function to trigger when any of the partici- mode.
pating axes exceeds the threshold. For inactivity detection, all
Register 0x2C BW_RATE (Read/Write)
participating axes are logically AND ed, causing the inactivity
D7 D6 D5 D4 D3 D2 D1 D0
function to trigger only if all participating axes are below the
0 0 0 LOW_POWER Rate
threshold for the specified time.
LOW_POWER Bit
Register 0x28 THRESH_FF (Read/Write)
A setting of 0 in the LOW_POWER bit selects normal operation,
The THRESH_FF register is eight bits and holds the threshold
and a setting of 1 selects reduced power operation, which has
value, in unsigned format, for free-fall detection. The acceleration on
somewhat higher noise (see the Power Modes section for details).
all axes is compared with the value in THRESH_FF to determine if
a free-fall event occurred. The scale factor is 62.5 mg/LSB. Note
Rate Bits
that a value of 0 mg may result in undesirable behavior if the free-
These bits select the device bandwidth and output data rate (see
fall interrupt is enabled. Values between 300 mg and 600 mg
Table 7 and Table 8 for details). The default value is 0x0A, which
(0x05 to 0x09) are recommended.
translates to a 100 Hz output data rate. An output data rate should
Register 0x29 TIME_FF (Read/Write)
be selected that is appropriate for the communication protocol
and frequency selected. Selecting too high of an output data rate with
The TIME_FF register is eight bits and stores an unsigned time
a low communication speed results in samples being discarded.
value representing the minimum time that the value of all axes
must be less than THRESH_FF to generate a free-fall interrupt.
Register 0x2D POWER_CTL (Read/Write)
The scale factor is 5 ms/LSB. A value of 0 may result in undesirable
D7 D6 D5 D4 D3 D2 D1 D0
behavior if the free-fall interrupt is enabled. Values between 100 ms
0 0 Link AUTO_SLEEP Measure Sleep Wakeup
and 350 ms (0x14 to 0x46) are recommended.
Link Bit
Register 0x2A TAP_AXES (Read/Write)
A setting of 1 in the link bit with both the activity and inactivity
D7 D6 D5 D4 D3 D2 D1 D0
functions enabled delays the start of the activity function until
0 0 0 0 Suppress TAP_X TAP_Y TAP_Z
enable enable enable
inactivity is detected. After activity is detected, inactivity detection
begins, preventing the detection of activity. This bit serially links
Suppress Bit
the activity and inactivity functions. When this bit is set to 0,
Setting the suppress bit suppresses double tap detection if
the inactivity and activity functions are concurrent. Additional
acceleration greater than the value in THRESH_TAP is present
information can be found in the Link Mode section.
between taps. See the Tap Detection section for more details.
When clearing the link bit, it is recommended that the part be
TAP_x Enable Bits
placed into standby mode and then set back to measurement
mode with a subsequent write. This is done to ensure that the
A setting of 1 in the TAP_X enable, TAP_Y enable, or TAP_Z
device is properly biased if sleep mode is manually disabled;
enable bit enables x-, y-, or z-axis participation in tap detection.
otherwise, the first few samples of data after the link bit is cleared
A setting of 0 excludes the selected axis from participation in
may have additional noise, especially if the device was asleep
tap detection.
when the bit was cleared.
Register 0x2B ACT_TAP_STATUS (Read Only)
D7 D6 D5 D4 D3 D2 D1 D0 AUTO_SLEEP Bit
0 ACT_X ACT_Y ACT_Z Asleep TAP_X TAP_Y TAP_Z
If the link bit is set, a setting of 1 in the AUTO_SLEEP bit enables
source source source source source source
the auto-sleep functionality. In this mode, the ADXL345 auto-
ACT_x Source and TAP_x Source Bits
matically switches to sleep mode if the inactivity function is
enabled and inactivity is detected (that is, when acceleration is
These bits indicate the first axis involved in a tap or activity
below the THRESH_INACT value for at least the time indicated
event. A setting of 1 corresponds to involvement in the event,
by TIME_INACT). If activity is also enabled, the ADXL345
and a setting of 0 corresponds to no involvement. When new
automatically wakes up from sleep after detecting activity and
data is available, these bits are not cleared but are overwritten by
returns to operation at the output data rate set in the BW_RATE
the new data. The ACT_TAP_STATUS register should be read
register. A setting of 0 in the AUTO_SLEEP bit disables automatic
before clearing the interrupt. Disabling an axis from participation
switching to sleep mode. See the description of the Sleep Bit in
clears the corresponding source bit when the next activity or
this section for more information on sleep mode.
single tap/double tap event occurs.
Rev. C | Page 25 of 40
ADXL345
If the link bit is not set, the AUTO_SLEEP feature is disabled Register 0x2E INT_ENABLE (Read/Write)
and setting the AUTO_SLEEP bit does not have an impact on D7 D6 D5 D4
device operation. Refer to the Link Bit section or the Link Mode DATA_READY SINGLE_TAP DOUBLE_TAP Activity
section for more information on utilization of the link feature.
D3 D2 D1 D0
Inactivity FREE_FALL Watermark Overrun
When clearing the AUTO_SLEEP bit, it is recommended that the
part be placed into standby mode and then set back to measure-
Setting bits in this register to a value of 1 enables their respective
ment mode with a subsequent write. This is done to ensure that
functions to generate interrupts, whereas a value of 0 prevents
the device is properly biased if sleep mode is manually disabled;
the functions from generating interrupts. The DATA_READY,
otherwise, the first few samples of data after the AUTO_SLEEP
watermark, and overrun bits enable only the interrupt output;
bit is cleared may have additional noise, especially if the device
the functions are always enabled. It is recommended that interrupts
was asleep when the bit was cleared.
be configured before enabling their outputs.
Measure Bit
Register 0x2F INT_MAP (R/ )
W
A setting of 0 in the measure bit places the part into standby mode,
D7 D6 D5 D4
and a setting of 1 places the part into measurement mode. The
DATA_READY SINGLE_TAP DOUBLE_TAP Activity
ADXL345 powers up in standby mode with minimum power
D3 D2 D1 D0
consumption.
Inactivity FREE_FALL Watermark Overrun
Sleep Bit
Any bits set to 0 in this register send their respective interrupts to
A setting of 0 in the sleep bit puts the part into the normal mode
the INT1 pin, whereas bits set to 1 send their respective interrupts
of operation, and a setting of 1 places the part into sleep mode.
to the INT2 pin. All selected interrupts for a given pin are OR ed.
Sleep mode suppresses DATA_READY, stops transmission of data
Register 0x30 INT_SOURCE (Read Only)
to FIFO, and switches the sampling rate to one specified by the
D7 D6 D5 D4
wakeup bits. In sleep mode, only the activity function can be used.
DATA_READY SINGLE_TAP DOUBLE_TAP Activity
When the DATA_READY interrupt is suppressed, the output
D3 D2 D1 D0
data registers (Register 0x32 to Register 0x37) are still updated
Inactivity FREE_FALL Watermark Overrun
at the sampling rate set by the wakeup bits (D1:D0).
Bits set to 1 in this register indicate that their respective functions
When clearing the sleep bit, it is recommended that the part be
have triggered an event, whereas a value of 0 indicates that the
placed into standby mode and then set back to measurement
corresponding event has not occurred. The DATA_READY,
mode with a subsequent write. This is done to ensure that the
watermark, and overrun bits are always set if the corresponding
device is properly biased if sleep mode is manually disabled;
events occur, regardless of the INT_ENABLE register settings,
otherwise, the first few samples of data after the sleep bit is
and are cleared by reading data from the DATAX, DATAY, and
cleared may have additional noise, especially if the device was
DATAZ registers. The DATA_READY and watermark bits may
asleep when the bit was cleared.
require multiple reads, as indicated in the FIFO mode descriptions
Wakeup Bits
in the FIFO section. Other bits, and the corresponding interrupts,
These bits control the frequency of readings in sleep mode as
are cleared by reading the INT_SOURCE register.
described in Table 20.
Register 0x31 DATA_FORMAT (Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Table 20. Frequency of Readings in Sleep Mode
SELF_TEST SPI INT_INVERT 0 FULL_RES Justify Range
Setting
D1 D0 Frequency (Hz)
The DATA_FORMAT register controls the presentation of data
0 0 8
to Register 0x32 through Register 0x37. All data, except that for
0 1 4
the ą16 g range, must be clipped to avoid rollover.
1 0 2
SELF_TEST Bit
1 1 1
A setting of 1 in the SELF_TEST bit applies a self-test force to
the sensor, causing a shift in the output data. A value of 0 disables
the self-test force.
SPI Bit
A value of 1 in the SPI bit sets the device to 3-wire SPI mode,
and a value of 0 sets the device to 4-wire SPI mode.
Rev. C | Page 26 of 40
ADXL345
INT_INVERT Bit Table 22. FIFO Modes
Setting
A value of 0 in the INT_INVERT bit sets the interrupts to active
D7 D6 Mode Function
high, and a value of 1 sets the interrupts to active low.
0 0 Bypass FIFO is bypassed.
FULL_RES Bit
0 1 FIFO FIFO collects up to 32 values and then
stops collecting data, collecting new data
When this bit is set to a value of 1, the device is in full resolution
only when FIFO is not full.
mode, where the output resolution increases with the g range
1 0 Stream FIFO holds the last 32 data values. When
set by the range bits to maintain a 4 mg/LSB scale factor. When
FIFO is full, the oldest data is overwritten
the FULL_RES bit is set to 0, the device is in 10-bit mode, and
with newer data.
the range bits determine the maximum g range and scale factor.
1 1 Trigger When triggered by the trigger bit, FIFO
holds the last data samples before the
Justify Bit
trigger event and then continues to collect
A setting of 1 in the justify bit selects left-justified (MSB) mode,
data until full. New data is collected only
and a setting of 0 selects right-justified mode with sign extension.
when FIFO is not full.
Range Bits
Trigger Bit
These bits set the g range as described in Table 21.
A value of 0 in the trigger bit links the trigger event of trigger mode
to INT1, and a value of 1 links the trigger event to INT2.
Table 21. g Range Setting
Samples Bits
Setting
D1 D0 g Range
The function of these bits depends on the FIFO mode selected
0 0 ą2 g
(see Table 23). Entering a value of 0 in the samples bits
0 1 ą4 g
immediately sets the watermark status bit in the INT_SOURCE
1 0 ą8 g
register, regardless of which FIFO mode is selected. Undesirable
1 1 ą16 g
operation may occur if a value of 0 is used for the samples bits
when trigger mode is used.
Register 0x32 to Register 0x37 DATAX0, DATAX1,
Table 23. Samples Bits Functions
DATAY0, DATAY1, DATAZ0, DATAZ1 (Read Only)
FIFO Mode Samples Bits Function
These six bytes (Register 0x32 to Register 0x37) are eight bits
Bypass None.
each and hold the output data for each axis. Register 0x32 and
FIFO Specifies how many FIFO entries are needed to
Register 0x33 hold the output data for the x-axis, Register 0x34 and
trigger a watermark interrupt.
Register 0x35 hold the output data for the y-axis, and Register 0x36
Stream Specifies how many FIFO entries are needed to
and Register 0x37 hold the output data for the z-axis. The output
trigger a watermark interrupt.
data is twos complement, with DATAx0 as the least significant
Trigger Specifies how many FIFO samples are retained in
byte and DATAx1 as the most significant byte, where x represent X, the FIFO buffer before a trigger event.
Y, or Z. The DATA_FORMAT register (Address 0x31) controls
0x39 FIFO_STATUS (Read Only)
the format of the data. It is recommended that a multiple-byte
D7 D6 D5 D4 D3 D2 D1 D0
read of all registers be performed to prevent a change in data
FIFO_TRIG 0 Entries
between reads of sequential registers.
FIFO_TRIG Bit
Register 0x38 FIFO_CTL (Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
A 1 in the FIFO_TRIG bit corresponds to a trigger event occurring,
FIFO_MODE Trigger Samples
and a 0 means that a FIFO trigger event has not occurred.
Entries Bits
FIFO_MODE Bits
These bits report how many data values are stored in FIFO.
These bits set the FIFO mode, as described in Table 22.
Access to collect the data from FIFO is provided through the
DATAX, DATAY, and DATAZ registers. FIFO reads must be
done in burst or multiple-byte mode because each FIFO level is
cleared after any read (single- or multiple-byte) of FIFO. FIFO
stores a maximum of 32 entries, which equates to a maximum
of 33 entries available at any given time because an additional
entry is available at the output filter of the device.
Rev. C | Page 27 of 40
ADXL345
APPLICATIONS INFORMATION
TAP DETECTION
POWER SUPPLY DECOUPLING
The tap interrupt function is capable of detecting either single
A 1 �F tantalum capacitor (C ) at V and a 0.1 �F ceramic capacitor
S S
or double taps. The following parameters are shown in Figure 46
(C ) at V placed close to the ADXL345 supply pins is
I/O DD I/O
for a valid single and valid double tap event:
recommended to adequately decouple the accelerometer from
noise on the power supply. If additional decoupling is necessary,
" The tap detection threshold is defined by the THRESH_TAP
a resistor or ferrite bead, no larger than 100 �, in series with V
S
register (Address 0x1D).
may be helpful. Additionally, increasing the bypass capacitance
" The maximum tap duration time is defined by the DUR
on V to a 10 �F tantalum capacitor in parallel with a 0.1 �F
S
register (Address 0x21).
ceramic capacitor may also improve noise.
" The tap latency time is defined by the latent register
Care should be taken to ensure that the connection from the (Address 0x22) and is the waiting period from the end
ADXL345 ground to the power supply ground has low impedance of the first tap until the start of the time window, when a
because noise transmitted through ground has an effect similar second tap can be detected, which is determined by the
to noise transmitted through V . It is recommended that V and value in the window register (Address 0x23).
S S
V be separate supplies to minimize digital clocking noise " The interval after the latency time (set by the latent register) is
DD I/O
on the V supply. If this is not possible, additional filtering of defined by the window register. Although a second tap must
S
the supplies, as previously mentioned, may be necessary. begin after the latency time has expired, it need not finish
VS VDD I/O before the end of the time defined by the window register.
CS CIO
FIRST TAP SECOND TAP
VS VDD I/O
ADXL345
SDA/SDI/SDIO
THRESHOLD
3- OR 4-WIRE
(THRESH_TAP)
SDO/ALT ADDRESS
INT1
INTERRUPT
SPI OR I2C
CONTROL SCL/SCLK
INTERFACE
INT2
GND CS
TIME LIMIT FOR
TAPS (DUR)
Figure 44. Application Diagram
TIME WINDOW FOR
LATENCY
SECOND TAP (WINDOW)
TIME
(LATENT)
MECHANICAL CONSIDERATIONS FOR MOUNTING
The ADXL345 should be mounted on the PCB in a location
SINGLE TAP DOUBLE TAP
INTERRUPT INTERRUPT
close to a hard mounting point of the PCB to the case. Mounting
the ADXL345 at an unsupported PCB location, as shown in
Figure 46. Tap Interrupt Function with Valid Single and Double Taps
Figure 45, may result in large, apparent measurement errors
due to undampened PCB vibration. Locating the accelerometer
If only the single tap function is in use, the single tap interrupt
near a hard mounting point ensures that any PCB vibration at
is triggered when the acceleration goes below the threshold, as
the accelerometer is above the accelerometer s mechanical sensor
long as DUR has not been exceeded. If both single and double
resonant frequency and, therefore, effectively invisible to the
tap functions are in use, the single tap interrupt is triggered
accelerometer. Multiple mounting points, close to the sensor,
when the double tap event has been either validated or
and/or a thicker PCB also help to reduce the effect of system
invalidated.
resonance on the performance of the sensor.
ACCELEROMETERS
PCB
MOUNTING POINTS
Figure 45. Incorrectly Placed Accelerometers
Rev. C | Page 28 of 40
HI BW
X
07925-016
INTERRUPTS
07925-037
07925-036
ADXL345
Several events can occur to invalidate the second tap of a double Single taps, double taps, or both can be detected by setting the
tap event. First, if the suppress bit in the TAP_AXES register respective bits in the INT_ENABLE register (Address 0x2E).
(Address 0x2A) is set, any acceleration spike above the threshold Control over participation of each of the three axes in single tap/
during the latency time (set by the latent register) invalidates double tap detection is exerted by setting the appropriate bits in
the double tap detection, as shown in Figure 47. the TAP_AXES register (Address 0x2A). For the double tap
function to operate, both the latent and window registers must
INVALIDATES DOUBLE TAP IF
SUPRESS BIT SET
be set to a nonzero value.
Every mechanical system has somewhat different single tap/
double tap responses based on the mechanical characteristics of
the system. Therefore, some experimentation with values for the
DUR, latent, window, and THRESH_TAP registers is required.
In general, a good starting point is to set the DUR register to a
TIME LIMIT value greater than 0x10 (10 ms), the latent register to a value greater
FOR TAPS LATENCY TIME WINDOW FOR SECOND
(DUR) TIME (LATENT) TAP (WINDOW) than 0x10 (20 ms), the window register to a value greater than
Figure 47. Double Tap Event Invalid Due to High g Event 0x40 (80 ms), and the THRESH_TAP register to a value greater
When the Suppress Bit Is Set
than 0x30 (3 g). Setting a very low value in the latent, window, or
THRESH_TAP register may result in an unpredictable response
A double tap event can also be invalidated if acceleration above
due to the accelerometer picking up echoes of the tap inputs.
the threshold is detected at the start of the time window for the
second tap (set by the window register). This results in an invalid
After a tap interrupt has been received, the first axis to exceed
double tap at the start of this window, as shown in Figure 48.
the THRESH_TAP level is reported in the ACT_TAP_STATUS
Additionally, a double tap event can be invalidated if an accel-
register (Address 0x2B). This register is never cleared but is
eration exceeds the time limit for taps (set by the DUR register),
overwritten with new data.
resulting in an invalid double tap at the end of the DUR time
THRESHOLD
limit for the second tap event, also shown in Figure 48.
The lower output data rates are achieved by decimating a common
INVALIDATES DOUBLE TAP
sampling frequency inside the device. The activity, free-fall, and
AT START OF WINDOW
single tap/double tap detection functions without improved tap
enabled are performed using undecimated data. Because the
bandwidth of the output data varies with the data rate and is
lower than the bandwidth of the undecimated data, the high
frequency and high g data that is used to determine activity,
free-fall, and single tap/double tap events may not be present
if the output of the accelerometer is examined. This may result
TIME LIMIT
FOR TAPS
in functions triggering when acceleration data does not appear
(DUR)
to meet the conditions set by the user for the corresponding
TIME LIMIT
FOR TAPS
LATENCY TIME WINDOW FOR function.
(DUR)
TIME SECOND TAP (WINDOW)
(LATENT)
LINK MODE
TIME LIMIT
FOR TAPS
The function of the link bit is to reduce the number of activity
(DUR)
interrupts that the processor must service by setting the device
to look for activity only after inactivity. For proper operation of
this feature, the processor must still respond to the activity and
inactivity interrupts by reading the INT_SOURCE register
INVALIDATES
(Address 0x30) and, therefore, clearing the interrupts. If an activity
DOUBLE TAP AT
END OF DUR
interrupt is not cleared, the part cannot go into autosleep mode.
The asleep bit in the ACT_TAP_STATUS register (Address 0x2B)
Figure 48. Tap Interrupt Function with Invalid Double Taps
indicates if the part is asleep.
Rev. C | Page 29 of 40
HI BW
X
07925-038
HI BW
X
HI BW
X
07925-039
ADXL345
The values measured for X and Y correspond to the x- and y-axis
0g 0g
SLEEP MODE VS. LOW POWER MODE
offset, and compensation is done by subtracting those values from
In applications where a low data rate and low power consumption
the output of the accelerometer to obtain the actual acceleration:
is desired (at the expense of noise performance), it is recommended
that low power mode be used. The use of low power mode preserves X = X - X
ACTUAL MEAS 0g
the functionality of the DATA_READY interrupt and the FIFO
Y = Y - Y
ACTUAL MEAS 0g
for postprocessing of the acceleration data. Sleep mode, while
Because the z-axis measurement was done in a +1 g field, a no-turn
offering a low data rate and power consumption, is not intended
or single-point calibration scheme assumes an ideal sensitivity,
for data acquisition.
S for the z-axis. This is subtracted from Z to attain the z-axis
Z +1g
However, when sleep mode is used in conjunction with the
offset, which is then subtracted from future measured values to
AUTO_SLEEP mode and the link mode, the part can automatically
obtain the actual value:
switch to a low power, low sampling rate mode when inactivity
Z = Z - S
0g +1g Z
is detected. To prevent the generation of redundant inactivity
interrupts, the inactivity interrupt is automatically disabled Z = Z - Z
ACTUAL MEAS 0g
and activity is enabled. When the ADXL345 is in sleep mode, the
The ADXL345 can automatically compensate the output for offset
host processor can also be placed into sleep mode or low power
by using the offset registers (Register 0x1E, Register 0x1F, and
mode to save significant system power. When activity is detected,
Register 0x20). These registers contain an 8-bit, twos complement
the accelerometer automatically switches back to the original
value that is automatically added to all measured acceleration
data rate of the application and provides an activity interrupt
values, and the result is then placed into the DATA registers.
that can be used to wake up the host processor. Similar to when
Because the value placed in an offset register is additive, a negative
inactivity occurs, detection of activity events is disabled and
value is placed into the register to eliminate a positive offset and
inactivity is enabled.
vice versa for a negative offset. The register has a scale factor of
15.6 mg/LSB and is independent of the selected g-range.
OFFSET CALIBRATION
As an example, assume that the ADXL345 is placed into full-
Accelerometers are mechanical structures containing elements
resolution mode with a sensitivity of typically 256 LSB/g. The
that are free to move. These moving parts can be very sensitive
part is oriented such that the z-axis is in the field of gravity and
to mechanical stresses, much more so than solid-state electronics.
x-, y-, and z-axis outputs are measured as +10 LSB, -13 LSB,
The 0 g bias or offset is an important accelerometer metric because
and +9 LSB, respectively. Using the previous equations, X is
it defines the baseline for measuring acceleration. Additional 0g
+10 LSB, Y is -13 LSB, and Z is +9 LSB. Each LSB of output
stresses can be applied during assembly of a system containing 0g 0g
in full-resolution is 3.9 mg or one-quarter of an LSB of the
an accelerometer. These stresses can come from, but are not
offset register. Because the offset register is additive, the 0 g
limited to, component soldering, board stress during mounting,
values are negated and rounded to the nearest LSB of the offset
and application of any compounds on or over the component. If
register:
calibration is deemed necessary, it is recommended that calibration
be performed after system assembly to compensate for these effects.
X = -Round(10/4) = -3 LSB
OFFSET
A simple method of calibration is to measure the offset while
Y = -Round(-13/4) = 3 LSB
OFFSET
assuming that the sensitivity of the ADXL345 is as specified in
Z = -Round(9/4) = -2 LSB
OFFSET
Table 1. The offset can then be automatically accounted for by
These values are programmed into the OFSX, OFSY, and OFXZ
using the built-in offset registers. This results in the data acquired
registers, respectively, as 0xFD, 0x03 and 0xFE. As with all
from the DATA registers already compensating for any offset.
registers in the ADXL345, the offset registers do not retain the
In a no-turn or single-point calibration scheme, the part is oriented
value written into them when power is removed from the part.
such that one axis, typically the z-axis, is in the 1 g field of gravity
Power-cycling the ADXL345 returns the offset registers to their
and the remaining axes, typically the x- and y-axis, are in a 0 g
default value of 0x00.
field. The output is then measured by taking the average of a
Because the no-turn or single-point calibration method assumes an
series of samples. The number of samples averaged is a choice of
ideal sensitivity in the z-axis, any error in the sensitivity results in
the system designer, but a recommended starting point is 0.1 sec
offset error. For instance, if the actual sensitivity was 250 LSB/g
worth of data for data rates of 100 Hz or greater. This corresponds
in the previous example, the offset would be 15 LSB, not 9 LSB.
to 10 samples at the 100 Hz data rate. For data rates less than
To help minimize this error, an additional measurement point
100 Hz, it is recommended that at least 10 samples be averaged
can be used with the z-axis in a 0 g field and the 0 g measurement
together. These values are stored as X , Y , and Z for the 0 g
0g 0g +1g
can be used in the Z equation.
ACTUAL
measurements on the x- and y-axis and the 1 g measurement on
the z-axis, respectively.
Rev. C | Page 30 of 40
ADXL345
Next, self-test should be enabled by setting Bit D7 (SELF_TEST) of
USING SELF-TEST
the DATA_FORMAT register (Address 0x31). The output needs
The self-test change is defined as the difference between the
some time (about four samples) to settle after enabling self-test.
acceleration output of an axis with self-test enabled and the
After allowing the output to settle, several samples of the x-, y-,
acceleration output of the same axis with self-test disabled (see
and z-axis acceleration data should be taken again and averaged. It
Endnote 4 of Table 1). This definition assumes that the sensor
is recommended that the same number of samples be taken for
does not move between these two measurements, because if the
this average as was previously taken. These averaged values should
sensor moves, a non self-test related shift corrupts the test.
again be stored and labeled appropriately as the value with self-
Proper configuration of the ADXL345 is also necessary for an
test enabled, that is, X , Y , and Z . Self-test can then be
ST_ON ST_ON ST_ON
accurate self-test measurement. The part should be set with a
disabled by clearing Bit D7 (SELF_TEST) of the DATA_FORMAT
data rate of 100 Hz through 800 Hz, or 3200 Hz. This is done by
register (Address 0x31).
ensuring that a value of 0x0A through 0x0D, or 0x0F is written
With the stored values for self-test enabled and disabled, the
into the rate bits (Bit D3 through Bit D0) in the BW_RATE
self-test change is as follows:
register (Address 0x2C). The part also must be placed into
normal power operation by ensuring the LOW_POWER bit in X = X - X
ST ST_ON ST_OFF
the BW_RATE register is cleared (LOW_POWER bit = 0) for
Y = Y - Y
ST ST_ON ST_OFF
accurate self-test measurements. It is recommended that the
Z = Z - Z
ST ST_ON ST_OFF
part be set to full-resolution, 16 g mode to ensure that there is
Because the measured output for each axis is expressed in LSBs,
sufficient dynamic range for the entire self-test shift. This is done
X , Y , and Z are also expressed in LSBs. These values can be
by setting Bit D3 of the DATA_FORMAT register (Address 0x31) ST ST ST
converted to g s of acceleration by multiplying each value by the
and writing a value of 0x03 to the range bits (Bit D1 and Bit D0) of
the DATA_FORMAT register (Address 0x31). This results in a high 3.9 mg/LSB scale factor, if configured for full-resolution mode.
dynamic range for measurement and a 3.9 mg/LSB scale factor. Additionally, Table 15 through Table 18 correspond to the self-test
range converted to LSBs and can be compared with the measured
After the part is configured for accurate self-test measurement,
self-test change when operating at a V of 2.5 V. For other voltages,
S
several samples of x-, y-, and z-axis acceleration data should be
the minimum and maximum self-test output values should be
retrieved from the sensor and averaged together. The number
adjusted based on (multiplied by) the scale factors shown in
of samples averaged is a choice of the system designer, but a
Table 14. If the part was placed into ą2 g, 10-bit or full-resolution
recommended starting point is 0.1 sec worth of data for data
mode, the values listed in Table 15 should be used. Although
rates of 100 Hz or greater. This corresponds to 10 samples at
the fixed 10-bit mode or a range other than 16 g can be used, a
the 100 Hz data rate. For data rates less than 100 Hz, it is
different set of values, as indicated in Table 16 through Table 18,
recommended that at least 10 samples be averaged together. The
would need to be used. Using a range below 8 g may result in
averaged values should be stored and labeled appropriately as
insufficient dynamic range and should be considered when
the self-test disabled data, that is, X , Y , and Z .
ST_OFF ST_OFF ST_OFF
selecting the range of operation for measuring self-test.
If the self-test change is within the valid range, the test is considered
successful. Generally, a part is considered to pass if the minimum
magnitude of change is achieved. However, a part that changes
by more than the maximum magnitude is not necessarily a failure.
Another effective method for using the self-test to verify accel-
erometer functionality is to toggle the self test at a certain rate
and then perform an FFT on the output. The FFT should have a
corresponding tone at the frequency the self-test was toggled.
Using an FFT like this removes the dependency of the test on
supply voltage and on self-test magnitude, which can vary within
a rather wide range.
Rev. C | Page 31 of 40
ADXL345
For a range of ą2 g, the LSB is Bit D6 of the DATAx0 register;
DATA FORMATTING OF UPPER DATA RATES
for ą4 g, Bit D5 of the DATAx0 register; for ą8 g, Bit D4 of the
Formatting of output data at the 3200 Hz and 1600 Hz output
DATAx0 register; and for ą16 g, Bit D3 of the DATAx0 register.
data rates changes depending on the mode of operation (full-
This is shown in Figure 50.
resolution or fixed 10-bit) and the selected output range.
The use of 3200 Hz and 1600 Hz output data rates for fixed 10-
When using the 3200 Hz or 1600 Hz output data rates in full-
bit operation in the ą4 g, ą8 g, and ą16 g output ranges
resolution or ą2 g, 10-bit operation, the LSB of the output data-
provides an LSB that is valid and that changes according to the
word is always 0. When data is right justified, this corresponds
applied acceleration. Therefore, in these modes of operation, Bit
to Bit D0 of the DATAx0 register, as shown in Figure 49. When
D0 is not always 0 when output data is right justified and Bit D6
data is left justified and the part is operating in ą2 g, 10-bit mode,
is not always 0 when output data is left justified. Operation at
the LSB of the output data-word is Bit D6 of the DATAx0 register.
any data rate of 800 Hz or lower also provides a valid LSB in all
In full-resolution operation when data is left justified, the location
ranges and modes that changes according to the applied
of the LSB changes according to the selected output range.
acceleration.
DATAx1 REGISTER DATAx0 REGISTER
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 0
OUTPUT DATA-WORD FOR
OUTPUT DATA-WORD FOR ALL
ą16g, FULL-RESOLUTION MODE.
10-BIT MODES AND THE ą2g,
FULL-RESOLUTION MODE.
THE ą4g AND ą8g FULL-RESOLUTION MODES HAVE THE SAME LSB LOCATION AS THE ą2g
AND ą16g FULL-RESOLUTION MODES, BUT THE MSB LOCATION CHANGES TO BIT D2 AND
BIT D3 OF THE DATAX1 REGISTER FOR ą4g AND ą8g, RESPECTIVELY.
Figure 49. Data Formatting of Full-Resolution and ą2 g, 10-Bit Modes of Operation When Output Data Is Right Justified
DATAx1 REGISTER DATAx0 REGISTER
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 0
LSB FOR ą2g, FULL-RESOLUTION
AND ą2g, 10-BIT MODES.
MSB FOR ALL MODES
OF OPERATION WHEN
LSB FOR ą4g, FULL-RESOLUTION MODE.
LEFT JUSTIFIED.
LSB FOR ą8g, FULL-RESOLUTION MODE.
LSB FOR ą16g, FULL-RESOLUTION MODE.
FOR 3200Hz AND 1600Hz OUTPUT DATA RATES, THE LSB IN THESE MODES IS ALWAYS 0.
ADDITIONALLY, ANY BITS TO THE RIGHT OF THE LSB ARE ALWAYS 0 WHEN THE OUTPUT
DATA IS LEFT JUSTIFIED.
Figure 50. Data Formatting of Full-Resolution and ą2 g, 10-Bit Modes of Operation When Output Data Is Left Justified
Rev. C | Page 32 of 40
07925-145
07925-146
ADXL345
10k
NOISE PERFORMANCE
X-AXIS
Y-AXIS
The specification of noise shown in Table 1 corresponds to
Z-AXIS
the typical noise performance of the ADXL345 in normal power
operation with an output data rate of 100 Hz (LOW_POWER bit
1k
(D4) = 0, rate bits (D3:D0) = 0xA in the BW_RATE register,
Address 0x2C). For normal power operation at data rates below
100 Hz, the noise of the ADXL345 is equivalent to the noise at
100 Hz ODR in LSBs. For data rates greater than 100 Hz, the
100
noise increases roughly by a factor of "2 per doubling of the data
rate. For example, at 400 Hz ODR, the noise on the x- and y-axes
is typically less than 1.5 LSB rms, and the noise on the z-axis is
typically less than 2.2 LSB rms.
10
0.01 0.1 1 10 100 1k 10k
For low power operation (LOW_POWER bit (D4) = 1 in the
AVERAGING PERIOD, (s)
BW_RATE register, Address 0x2C), the noise of the ADXL345
Figure 52. Root Allan Deviation
is constant for all valid data rates shown in Table 8. This value is
130
typically less than 1.8 LSB rms for the x- and y-axes and typically
less than 2.6LSB rms for the z-axis.
120
The trend of noise performance for both normal power and low
X-AXIS
110 Y-AXIS
power modes of operation of the ADXL345 is shown in Figure 51.
Z-AXIS
Figure 52 shows the typical Allan deviation for the ADXL345.
100
The 1/f corner of the device, as shown in this figure, is very low,
allowing absolute resolution of approximately 100 �g (assuming
90
that there is sufficient integration time). Figure 52 also shows
that the noise density is 290 �g/"Hz for the x-axis and y-axis
80
and 430 �g/"Hz for the z-axis.
Figure 53 shows the typical noise performance trend of the
70
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
ADXL345 over supply voltage. The performance is normalized
SUPPLY VOLTAGE, VS (V)
to the tested and specified supply voltage, V = 2.5 V. In general,
S
Figure 53. Normalized Noise vs. Supply Voltage, V
S
noise decreases as supply voltage is increased. It should be noted, as
shown in Figure 51, that the noise on the z-axis is typically higher
OPERATION AT VOLTAGES OTHER THAN 2.5 V
than on the x-axis and y-axis; therefore, while they change roughly
The ADXL345 is tested and specified at a supply voltage of
the same in percentage over supply voltage, the magnitude of change
V = 2.5 V; however, it can be powered with V as high as 3.6 V
S S
on the z-axis is greater than the magnitude of change on the
or as low as 2.0 V. Some performance parameters change as the
x-axis and y-axis.
supply voltage changes: offset, sensitivity, noise, self-test, and
5.0
supply current.
X-AXIS, LOW POWER
4.5
Y-AXIS, LOW POWER
Due to slight changes in the electrostatic forces as supply voltage
Z-AXIS, LOW POWER
4.0
X-AXIS, NORMAL POWER
is varied, the offset and sensitivity change slightly. When operating
Y-AXIS, NORMAL POWER
3.5
Z-AXIS, NORMAL POWER at a supply voltage of V = 3.3 V, the x- and y-axis offset is typically
S
3.0 25 mg higher than at Vs = 2.5 V operation. The z-axis is typically
20 mg lower when operating at a supply voltage of 3.3 V than when
2.5
operating at V = 2.5 V. Sensitivity on the x- and y-axes typically
S
2.0
shifts from a nominal 256 LSB/g (full-resolution or ą2 g, 10-bit
1.5
operation) at V = 2.5 V operation to 265 LSB/g when operating
S
1.0
with a supply voltage of 3.3 V. The z-axis sensitivity is unaffected by
0.5
a change in supply voltage and is the same at V = 3.3 V operation
S
0 as it is at V = 2.5 V operation. Simple linear interpolation can be
S
3.13 6.25 12.50 25 50 100 200 400 800 1600 3200
used to determine typical shifts in offset and sensitivity at other
OUTPUT DATA RATE (Hz)
supply voltages.
Figure 51. Noise vs. Output Data Rate for Normal and Low Power Modes,
Full-Resolution (256 LSB/g)
Rev. C | Page 33 of 40
ALLAN DEVIATION (�
g
)
07925-251
PERCENTAGE OF NORMALIZED NOISE (%)
07925-252
OUTPUT NOISE (LSB rms)
07925-250
ADXL345
140
Changes in noise performance, self-test response, and supply
current are discussed elsewhere throughout the data sheet. For
120
noise performance, the Noise Performance section should be
reviewed. The Using Self-Test section discusses both the
100
operation of self-test over voltage, a square relationship with
80
supply voltage, as well as the conversion of the self-test response
0.10Hz
in g s to LSBs. Finally, Figure 33 shows the impact of supply
0.20Hz
60
0.39Hz
voltage on typical current consumption at a 100 Hz output data
0.78Hz
1.56Hz
rate, with all other output data rates following the same trend.
40
3.13Hz
6.25Hz
OFFSET PERFORMANCE AT LOWEST DATA RATES
20
The ADXL345 offers a large number of output data rates and
0
bandwidths, designed for a large range of applications. However,
25 35 45 55 65 75 85
at the lowest data rates, described as those data rates below 6.25 Hz,
TEMPERATURE (�C)
the offset performance over temperature can vary significantly Figure 55. Typical Y-Axis Output vs. Temperature at Lower Data Rates,
Normalized to 100 Hz Output Data Rate, V = 2.5 V
S
from the remaining data rates. Figure 54, Figure 55, and Figure 56
140
show the typical offset performance of the ADXL345 over
temperature for the data rates of 6.25 Hz and lower. All plots
120
are normalized to the offset at 100 Hz output data rate; therefore,
100
a nonzero value corresponds to additional offset shift due to
temperature for that data rate.
80
When using the lowest data rates, it is recommended that the
0.10Hz
60
0.20Hz
operating temperature range of the device be limited to provide
0.39Hz
40
minimal offset shift across the operating temperature range. 0.78Hz
1.56Hz
Due to variability between parts, it is also recommended that
3.13Hz
20
6.25Hz
calibration over temperature be performed if any data rates
0
below 6.25 Hz are in use.
140
20
25 35 45 55 65 75 85
120 TEMPERATURE (�C)
Figure 56. Typical Z-Axis Output vs. Temperature at Lower Data Rates,
100
Normalized to 100 Hz Output Data Rate, V = 2.5 V
S
80
0.10Hz
0.20Hz
60
0.39Hz
0.78Hz
1.56Hz
40
3.13Hz
6.25Hz
20
0
25 35 45 55 65 75 85
TEMPERATURE (�C)
Figure 54. Typical X-Axis Output vs. Temperature at Lower Data Rates,
Normalized to 100 Hz Output Data Rate, V = 2.5 V
S
Rev. C | Page 34 of 40
NORMALIZED OUTPUT (LSB)
07925-057
NORMALIZED OUTPUT (LSB)
07925-058
NORMALIZED OUTPUT (LSB)
07925-056
ADXL345
AXES OF ACCELERATION SENSITIVITY
AZ
AY
AX
Figure 57. Axes of Acceleration Sensitivity (Corresponding Output Voltage Increases When Accelerated Along the Sensitive Axis)
XOUT = 1g
YOUT = 0g
ZOUT = 0g
TOP
GRAVITY
XOUT = 0g XOUT = 0g
YOUT = 1g YOUT = 1g
ZOUT = 0g ZOUT = 0g
XOUT = 1g
YOUT = 0g
ZOUT = 0g
XOUT = 0g XOUT = 0g
YOUT = 0g YOUT = 0g
ZOUT = 1g ZOUT = 1g
Figure 58. Output Response vs. Orientation to Gravity
Rev. C | Page 35 of 40
TOP
07925-021
TOP
07925-022
TOP
ADXL345
LAYOUT AND DESIGN RECOMMENDATIONS
Figure 59 shows the recommended printed wiring board land pattern. Figure 60 and Table 24 provide details about the recommended
soldering profile.
3.3400
1.0500
0.5500
0.2500
3.0500
5.3400
0.2500
1.1450
Figure 59. Recommended Printed Wiring Board Land Pattern (Dimensions shown in millimeters)
CRITICAL ZONE
tP
TL TO TP
TP
RAMP-UP
TL
tL
TSMAX
TSMIN
tS
RAMP-DOWN
PREHEAT
t25�C TO PEAK
TIME
Figure 60. Recommended Soldering Profile
Table 24. Recommended Soldering Profile1 , 2
Condition
Profile Feature Sn63/Pb37 Pb-Free
Average Ramp Rate from Liquid Temperature (T ) to Peak Temperature (T ) 3�C/sec maximum 3�C/sec maximum
L P
Preheat
Minimum Temperature (T ) 100�C 150�C
SMIN
Maximum Temperature (T ) 150�C 200�C
SMAX
Time from T to T (t ) 60 sec to 120 sec 60 sec to 180 sec
SMIN SMAX S
T to T Ramp-Up Rate 3�C/sec maximum 3�C/sec maximum
SMAX L
Liquid Temperature (T ) 183�C 217�C
L
Time Maintained Above T (t ) 60 sec to 150 sec 60 sec to 150 sec
L L
Peak Temperature (T ) 240 + 0/-5�C 260 + 0/-5�C
P
Time of Actual T - 5�C (t ) 10 sec to 30 sec 20 sec to 40 sec
P P
Ramp-Down Rate 6�C/sec maximum 6�C/sec maximum
Time 25�C to Peak Temperature 6 minutes maximum 8 minutes maximum
1
Based on JEDEC Standard J-STD-020D.1.
2
For best results, the soldering profile should be in accordance with the recommendations of the manufacturer of the solder paste used.
Rev. C | Page 36 of 40
07925-014
TEMPERATURE
07925-015
ADXL345
OUTLINE DIMENSIONS
3.00
PAD A1 BSC
0.49 BOTTOM VIEW
CORNER
0.813 � 0.50
1
13
14
0.80
5.00
BSC
BSC
0.50
8 6
7
TOP VIEW
1.01
0.49
0.79
1.00
1.50
0.74
END VIEW
0.95
0.69
0.85
SEATING
PLANE
Figure 61. 14-Terminal Land Grid Array [LGA]
(CC-14-1)
Solder Terminations Finish Is Au over Ni
Dimensions shown in millimeters
ORDERING GUIDE
Measurement Specified Package
Model1 Range (g) Voltage (V) Temperature Range Package Description Option
ADXL345BCCZ ą2, ą4, ą8, ą16 2.5 -40�C to +85�C 14-Terminal Land Grid Array [LGA] CC-14-1
ADXL345BCCZ-RL ą2, ą4, ą8, ą16 2.5 -40�C to +85�C 14-Terminal Land Grid Array [LGA] CC-14-1
ADXL345BCCZ-RL7 ą2, ą4, ą8, ą16 2.5 -40�C to +85�C 14-Terminal Land Grid Array [LGA] CC-14-1
EVAL-ADXL345Z Evaluation Board
EVAL-ADXL345Z-DB Evaluation Board
EVAL-ADXL345Z-M Analog Devices Inertial Sensor Evaluation
System, Includes ADXL345 Satellite
EVAL-ADXL345Z-S ADXL345 Satellite, Standalone
1
Z = RoHS Compliant Part.
Rev. C | Page 37 of 40
03-16-2010-A
ADXL345
NOTES
Rev. C | Page 38 of 40
ADXL345
NOTES
Rev. C | Page 39 of 40
ADXL345
NOTES
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
Analog Devices offers specific products designated for automotive applications; please consult your local Analog Devices sales representative for details. Standard products sold by
Analog Devices are not designed, intended, or approved for use in life support, implantable medical devices, transportation, nuclear, safety, or other equipment where malfunction
of the product can reasonably be expected to result in personal injury, death, severe property damage, or severe environmental harm. Buyer uses or sells standard products for use
in the above critical applications at Buyer's own risk and Buyer agrees to defend, indemnify, and hold harmless Analog Devices from any and all damages, claims, suits, or expenses
resulting from such unintended use.
�2009 2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07925-0-5/11(C)
Rev. C | Page 40 of 40

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