Xilinx Design Summary top Project Status (06/10/2013 - 10:42:41) Project File: w7s.xise Parser Errors: No Errors Module Name: top Implementation State: Fitted Target Device: xc2c256-6TQ144 Errors: No Errors Product Version:ISE 14.4 Warnings: 4 Warnings (4 new) Design Goal: Balanced Routing Results:   Design Strategy: Xilinx Default (unlocked) Timing Constraints:   Environment: System Settings Final Timing Score:      Detailed Reports [-] Report NameStatusGenerated ErrorsWarningsInfos Synthesis ReportCurrentPn 10. cze 10:42:11 201304 Warnings (4 new)0 Translation ReportCurrentPn 10. cze 10:42:17 2013000 CPLD Fitter Report (Text)CurrentPn 10. cze 10:42:25 201302 Warnings (2 new)1 Info (1 new) Power Report        Secondary Reports [-] Report NameStatusGenerated Post-Fit Simulation Model Report   Date Generated: 06/10/2013 - 10:42:41
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