15

u

13

12

11

10 9 8

7 6 5

4

3

2

1

0

System byt®

Condition oode register (OCR)

Field

T

—

S

M

—

1

—

X

N

Z

V

C

Reset

0

0

1

0

0

111

000

—

—

—

—

—

R/W

R/W

R

R/W

R/W

R

R/W

R

R/W

R/W

R/W

R/W

R/W

Bits

Name

Description

15

T

Trać® enable. When T is set. the processor pertorms a trać® exc®ption after ev©ry instmction.

13

S

Supervisor/us®r State. Indicates whether the processor is in supervisor or user modę

0    User modę

1    Supen/isor modę

12

M

Master/interrupt State. Cleared by on interrupt exception. It can be set by software during execution of the RTE or move to SR instmctions so the OS can emulat® an intermpt stack pointer.

10-8

I

Interrupt prioiity mask. Defines the cuirent intermpt priority. Intermpt requests ar© inhibited for all priority levels less than or equal to the current priority. except the edge-sensitive level-7 request. which cannot be masked.

7-0

CCR

Condition codę register. See Table 2-1.