AIS326DQ
MEMS inertial sensor
3-axis, low g accelerometer with digital output
Data Brief
Features
% 3.3 V single supply operation
% 1.8 V compatible IOs
% SPI digital output interface(a)
% 12 bit resolution
% Interrupt activated by motion
% Programmable interrupt threshold
QFPN-28
% Embedded self-test
% High shock survivability
% ECOPACK compliant (see Section 9)
The AIS326DQ has a user selectable full scale of
% Extended temperature range -40 C to +105 C
ą2 g, ą6 g and it is capable of measuring
acceleration over a bandwidth of 640 Hz for all
axes. The device bandwidth may be selected
Description
accordingly to the application requirements. The
The AIS326DQ is a three axes digital output
self-test capability allows the user to check the
accelerometer that includes a sensing element
functioning of the system.
and an IC interface able to take the information
The device is available in plastic quad flat
from the sensing element and to provide the
package no lead surface mount (QFPN) and it is
measured acceleration signals to the external
specified over a temperature range extending
world through an SPI serial interface.
from -40 C to +105 C.
The sensing element, capable of detecting the
The AIS326DQ may be used in non-safety
acceleration, is manufactured using a dedicated
automotive applications, such as:
process developed by ST to produce inertial
sensors and actuators in silicon.
% Anti-theft systems and inertial navigation
% Motion activated functions
The IC interface instead is manufactured using a
CMOS process that allows high level of
% Vibration monitoring and compensation
integration to design a dedicated circuit which is
% Tilt measurements
factory trimmed to better match the sensing
% Black boxes, event recorders
element characteristics.
Table 1. Device summary
Operating temperature
Order code Package Packing
range [ C]
AIS326DQ -40 to +105 QFPN-28 Tray
AIS326DQTR -40 to +105 QFPN-28 Tape and reel
a. I2C interface is also available.
August 2008 Rev 1 1/49
For further information contact your local STMicroelectronics sales office. www.st.com 49
Contents AIS326DQ
Contents
1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.2 QFPN-28 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2 Mechanical and electrical specifications . . . . . . . . . . . . . . . . . . . . . . . 10
2.1 Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3.1 SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.5 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.5.1 Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.5.2 Zero-g level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.5.3 Self test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3 Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1 Sensing element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2 IC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3 Factory calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4 Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5 Digital interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.1 SPI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.1.1 SPI Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1.2 SPI Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.1.3 SPI Read in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6 Register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.1 WHO_AM_I (0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.2 OFFSET_X (16h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
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AIS326DQ Contents
7.3 OFFSET_Y (17h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.4 OFFSET_Z (18h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.5 GAIN_X (19h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.6 GAIN_Y (1Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.7 GAIN_Z (1Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.8 CTRL_REG1 (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.9 CTRL_REG2 (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.10 CTRL_REG3 (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.11 HP_FILTER_RESET (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.12 STATUS_REG (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.13 OUTX_L (28h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.14 OUTX_H (29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.15 OUTY_L (2Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.16 OUTY_H (2Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.17 OUTZ_L (2Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.18 OUTZ_H (2Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.19 FF_WU_CFG (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.20 FF_WU_SRC (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.21 FF_WU_ACK (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.22 FF_WU_THS_L (34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.23 FF_WU_THS_H (35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.24 FF_WU_DURATION (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.25 DD_CFG (38h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.26 DD_SRC (39h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.27 DD_ACK (3Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.28 DD_THSI_L (3Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.29 DD_THSI_H (3Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.30 DD_THSE_L (3Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.31 DD_THSE_H (3Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
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Contents AIS326DQ
8 Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
8.1 Mechanical characteristics at 25 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
8.2 Mechanical characteristics at -40 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.3 Mechanical characteristics at 105 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.4 Mechanical characteristics derived from measurement in the -40 C to +105
C temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.5 Electro-mechanical characteristics at 25 C . . . . . . . . . . . . . . . . . . . . . . . 42
8.6 Electrical characteristics at 25 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.7 Electrical characteristics at -40 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.8 Electrical characteristics at 105 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9 Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9.1 General guidelines about soldering surface mount accelerometer . . . . . 44
9.2 PCB design guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9.2.1 PCB design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.3 Stencil design and solder paste application . . . . . . . . . . . . . . . . . . . . . . . 45
9.4 Process consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
10 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
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AIS326DQ List of tables
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 3. Mechanical characteristics @ Vdd = 3.3 V, T = -40 C to 105 C unless otherwise noted. 10
Table 4. Electrical characteristics @ Vdd=3.3 V, T = -40 C to 105 C unless otherwise noted . . . 12
Table 5. SPI slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 6. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 7. Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 8. Registers address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 9. Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 10. Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 11. OFFSET_X register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 12. OFFSET_X register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 13. OFFSET_Y register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 14. OFFSET_Y register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 15. OFFSET_Z register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 16. OFFSET_Z register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 17. GAIN_X register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 18. GAIN_X register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 19. GAIN_Y register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 20. GAIN_Y register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 21. GAIN_Z register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 22. GAIN_Z register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 23. CTRL_REG1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 24. CTRL_REG1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 25. CTRL_REG2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 26. CTRL_REG2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 27. CTRL_REG3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 28. CTRL_REG3 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 29. STATUS_REG register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 30. STATUS_REG register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 31. OUTX_L register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 32. OUTX_L register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 33. OUTX_H register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 34. OUTX_H register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 35. OUTY_L register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 36. OUTY_L register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 37. OUTY_H register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 38. OUTY_H register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 39. OUTZ_L register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 40. OUTZ_L register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 41. OUTZ_H register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 42. OUTZ_H register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 43. FF_WU_CFG register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 44. FF_WU_CFG register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 45. FF_WU_SRC register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 46. FF_WU_SRC register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 47. FF_WU_THS_L register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 48. FF_WU_THS_L register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5/49
List of tables AIS326DQ
Table 49. FF_WU_THS_H register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 50. FF_WU_THS_H register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 51. FF_WU_DURATION register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 52. FF_WU_DURATION register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 53. DD_CFG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 54. DD_CFG register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 55. DD_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 56. DD_SRC register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 57. DD_THSI_L register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 58. DD_THSI_L register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 59. DD_THSI_H register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 60. DD_THSI_H register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 61. DD_THSE_L register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 62. DD_THSE_L register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 63. DD_THSE_H register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 64. DD_THSE_H register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 65. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6/49
AIS326DQ List of figures
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 2. Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3. SPI slave timing diagram (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 4. AIS326DQ electrical connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 5. Read and write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 6. SPI read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 7. Multiple bytes SPI read protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 8. SPI Write protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 9. Multiple bytes SPI write protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 10. SPI read protocol in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 11. X-axis zero-g level at 3.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 12. X-axis sensitivity at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 13. Y-axis zero-g level at 3.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 14. Y-axis sensitivity at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 15. Z-axis zero-g level at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 16. Z-axis sensitivity at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 17. X-axis zero-g level at 3.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 18. X-axis sensitivity at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 19. Y-axis zero-g level at 3.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 20. Y-axis sensitivity at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 21. Z-axis zero-g level at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 22. Z-axis sensitivity at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 23. X-axis zero-g level at 3.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 24. X-axis sensitivity at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 25. Y-axis zero-g level at 3.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 26. Y-axis sensitivity at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 27. Z-axis zero-g level at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 28. Z-axis sensitivity at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 29. X-axis zero-g level change vs. temperature at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 30. X-axis sensitivity change vs. temperature at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 31. Y-axis zero-g level change vs. temperature at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 32. Y-axis sensitivity change vs. temperature at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 33. Z-axis zero-g level change vs. temperature at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 34. Z-axis sensitivity change vs. temperature at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 35. X and Y axes zero-g level as function of supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 36. X and Y axes sensitivity as function of supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 37. Z axis zero-g level as function of supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 38. Z axis sensitivity as function of supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 39. Current consumption in power-down mode (Vdd=3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 40. Current consumption in operational mode (Vdd=3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 41. Current consumption in power-down mode (Vdd=3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 42. Current consumption in operational mode (Vdd=3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 43. Current consumption in power-down mode (Vdd=3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 44. Current consumption in operational mode (Vdd=3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 45. Recommended land and solder mask design for QFPN packages. . . . . . . . . . . . . . . . . . . 45
Figure 46. QFPN-28 mechanical data and package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
7/49
Block diagram and pin description AIS326DQ
1 Block diagram and pin description
1.1 Block diagram
Figure 1. Block diagram
X+
Reconstruction
Ł"
Y+
Filter
CHARGE
CS
Z+
AMPLIFIER
SPC
DE
Reconstruction Regs
MUX
a Ł"
MUX SPI
SDO/SDI
Array
Filter
Z-
SDO
Y-
Reconstruction
X- Ł"
Filter
CONTROL LOGIC
RDY/INT
TRIMMING
&
SELF TEST REFERENCE CLOCK
CIRCUITS
INTERRUPT GEN.
1.2 QFPN-28 pin description
Figure 2. Pin connection
28 22
Z NC 1 21 NC
1
Y
GND Reserved
Vdd Vdd
AIS326DQ
Reserved Reserved
(TOP VIEW)
GND GND
X
RDY/INT CK
NC NC
7 15
DIRECTIONS OF THE
DETECTABLE
814
ACCELERATIONS
8/49
NC
NC
NC
NC
NC
NC
NC
CS
NC
NC
SPC
SDO
Vdd_IO
SDI/SDO
AIS326DQ Block diagram and pin description
Table 2. Pin description
Pin# Name Function
1 NC Internally not connected
2 GND 0 V supply
3 Vdd Power supply
4 Reserved Either leave unconnected or connect to GND
5 GND 0 V supply
6 RDY/INT Data ready/inertial wake-up and free-fall interrupt
7, 8 NC Internally not connected
9 SDO SPI serial data output
SDI/ SPI serial data input (SDI)
10
SDO 3-wire interface serial data output (SDO)
11 Vdd_IO Power supply for I/O pads
12 SPC SPI serial port clock
13 CS Chip select (logic 0: SPI enabled, logic 1: SPI disabled)
14, 15 NC Internally not connected
Optional external clock, if not used either leave unconnected or
16 CK
connect to GND
17 GND 0 V supply
18 Reserved Either leave unconnected or connect to Vdd_IO
19 Vdd Power supply
20 Reserved Connect to Vdd
21 - 28 NC Internally not connected
9/49
Mechanical and electrical specifications AIS326DQ
2 Mechanical and electrical specifications
2.1 Mechanical characteristics
Table 3. Mechanical characteristics @ Vdd = 3.3 V, T = -40 C to 105 C unless otherwise
noted(1)
Symbol Parameter Test conditions Min. Typ.(2) Max. Unit
FS bit set to 0 ą1.7 ą2.0
FS Measurement range(3) g
FS bit set to 1 ą5.3 ą6.0
Full-scale = ą2 g
1.0
T = 25 C, ODR1=40 Hz
Full-scale = ą2 g
2.0
T = 25 C, ODR2=160 Hz
Dres Device resolution mg
Full-scale = ą2 g
3.9
T = 25 C, ODR3 = 640 Hz
Full-scale = ą2 g
15.6
T = 25 C, ODR4 = 2560 Hz
Full-scale = ą2 g
952 1024 1096
12 bit representation
So Sensitivity LSb/g
Full-scale = ą6 g
316 340 364
12 bit representation(4)
Sensitivity change vs Full-scale = ą2 g
TCSo 0.025 %/C
temperature 12 bit representation
Full-scale = ą2 g
-100 100
X, Y axis
Full-scale = ą2 g
-200 200
Z axis
Zero-g level offset
Off mg
accuracy(5),(6)
Full-scale = ą6 g
-100 100
X, Y axis(4)
Full-scale = ą6 g
-200 200
Z axis(4)
Zero-g level change vs
TCOff Max delta from 25 C 0.2 mg/C
temperature
Best fit straight line
X, Y axis
ą2
Full-scale = ą2 g
ODR = 40 Hz
NL Non linearity(4) % FS
Best fit straight line
Z axis
ą3
Full-scale = ą2 g
ODR = 40 Hz
10/49
AIS326DQ Mechanical and electrical specifications
Table 3. Mechanical characteristics @ Vdd = 3.3 V, T = -40 C to 105 C unless otherwise
noted(1) (continued)
Symbol Parameter Test conditions Min. Typ.(2) Max. Unit
CrAx Cross axis(4) -5 5 %
Full-scale= ą2 g
110 210 310
X axis
Full-scale= ą2 g LSb
110 210 310
Y axis
Full-scale= ą2 g
70 160 250
Z axis
Vst Self-test output change(7),(8)
Full-scale= ą6 g
30 70 120
X axis
Full-scale= ą6 g LSb
30 70 120
Y axis
Full-scale= ą6 g
20 55 110
Z axis
BW System bandwidth(9) ODRx/4 Hz
TOP Operating temperature range -40 +105 C
Wh Product weight 0.2 gram
1. The product is factory calibrated at 3.3 V. Operation over 3.6 V is not recommended
2. Typical specifications are not guaranteed
3. Verified by wafer level test and specification of initial offset and sensitivity
4. Guaranteed by design
5. Zero-g level offset value after MSL3 preconditioning
6. Offset can be eliminated by enabling the built-in high pass filter (HPF)
7. Self test output changes with the power supply. Self-test output change is defined as OUTPUT[LSb](Self-test bit on
- OUTPUT[LSb](Self-test bit on CTRL_REG1=0). 1LSb = 1g/1024 at 12 bit representation, 2 g Full-scale
CTRL_REG1=1)
8. Output data reach 99% of final value after 5/ODR when enabling Self-test mode due to device filtering
9. ODRx is output data rate. Refer to Table 4 for specifications
11/49
Mechanical and electrical specifications AIS326DQ
2.2 Electrical characteristics
Table 4. Electrical characteristics @ Vdd=3.3 V, T = -40 C to 105 C unless otherwise noted(1)
Symbol Parameter Test conditions Min. Typ.(2) Max. Unit
Vdd Supply voltage 3.0 3.3 3.6 V
Vdd_IO I/O pads supply voltage(3) 1.71 Vdd V
Idd Supply current Vdd = 3.3 V 0.67 0.80 mA
Current consumption
IddPdn 210 A
in power-down mode
VIH Digital high level Input voltage(3) 0.8*Vdd_IO
V
VIL Digital low level Input voltage(3) 0.2*Vdd_IO
VOH High level output voltage(3) 0.9*Vdd_IO
V
VOL Low level output voltage(3) 0.1*Vdd_IO
ODR1 Output data rate 1 Dec factor = 512 40
ODR2 Output data rate 2 Dec factor = 128 160
Hz
ODR3 Output data rate 3 Dec factor = 32 640
ODR4 Output data rate 4 Dec factor = 8 2560
BW System bandwidth(4) ODRx/4 Hz
Ton Turn-on time(5) 5/ODRx s
TOP Operating temperature range -40 +105 C
1. The product is factory calibrated at 3.3 V. Operation over 3.6 V is not recommended
2. Typical specifications are not guaranteed
3. Guaranteed by design
4. Digital filter -3 dB frequency
5. Time to obtain valid data after exiting power-down mode
12/49
AIS326DQ Mechanical and electrical specifications
2.3 Communication interface characteristics
2.3.1 SPI - serial peripheral interface
Subject to general operating conditions for Vdd and TOP.
Table 5. SPI slave timing values
Value(1)
Symbol Parameter Unit
Min Max
tc(SPC) SPI clock cycle 125 ns
fc(SPC) SPI clock frequency 8 MHz
tsu(CS) CS setup time 5
th(CS) CS hold time 10
tsu(SI) SDI input setup time 5
th(SI) SDI input hold time 15 ns
tv(SO) SDO valid output time 55
th(SO) SDO output hold time 7
tdis(SO) SDO output disable time 50
1. Values are guaranteed at 8 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization
results, not tested in production
Figure 3. SPI slave timing diagram (2)
CS
(3) (3)
tc(SPC)
tsu(CS) th(CS)
SPC
(3) (3)
tsu(SI) th(SI)
LSB IN
SDI (3) MSB IN (3)
tv(SO) th(SO) tdis(SO)
(3) MSB OUT LSB OUT (3)
SDO
2. Measurement points are done at 0.2Vdd_IO and 0.8Vdd_IO, for both input and output port
3. When no communication is on-going, data on CS, SPC, SDI and SDO are driven by internal pull-up
resistors
13/49
Mechanical and electrical specifications AIS326DQ
2.4 Absolute maximum ratings
Stresses above those listed as absolute maximum ratings may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
Table 6. Absolute maximum ratings
Symbol Ratings Maximum value Unit
Vdd Supply voltage(1) -0.3 to 6.0 V
Vdd_IO I/O pins supply voltage(1) -0.3 to Vdd +0.1 V
Input voltage on any control pin(1)
Vin -0.3 to Vdd_IO +0.3 V
(CS, SPC, SDI/SDO, SDO, CK)
3000 g for 0.5 ms
APOW Acceleration (any axis, powered, Vdd = 3.3 V)
10000 g for 0.1 ms
3000 g for 0.5 ms
AUNP Acceleration (any axis, unpowered)
10000 g for 0.1 ms
TOP Operating temperature range -40 to +105 C
TSTG Storage temperature range -40 to +125 C
4.0 (HBM) kV
ESD Electrostatic discharge protection 200 (MM) V
1.5 (CDM) kV
1. Supply voltage on any pin should never exceed 6.0 V.
This is a mechanical shock sensitive device, improper handling can cause
permanent damages to the part
This is an ESD sensitive device, improper handling can cause permanent damages
to the part
14/49
AIS326DQ Mechanical and electrical specifications
2.5 Terminology
2.5.1 Sensitivity
Sensitivity describes the gain of the sensor and can be determined e.g. by applying 1 g
acceleration to it. As the sensor can measure DC accelerations this can be done easily by
pointing the axis of interest towards the center of the earth, noting the output value, rotating
the sensor by 180 degrees (point to the sky) and noting the output value again. By doing so,
ą1 g acceleration is applied to the sensor. Subtracting the larger output value from the
smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. This
value changes very little over temperature and also very little over time. The Sensitivity
tolerance describes the range of sensitivities of a large population of sensors.
2.5.2 Zero-g level
Zero-g level offset (Off) describes the deviation of an actual output signal from the ideal
output signal if there is no acceleration present. A sensor in a steady state on a horizontal
surface will measure 0 g in X axis and 0 g in Y axis whereas the Z axis will measure 1 g. The
output is ideally in the middle of the dynamic range of the sensor (content of OUT registers
00h, 00h with 16 bit representation, data expressed as 2 s complement number). A deviation
from ideal value in this case is called Zero-g offset. Offset is to some extent a result of stress
to a precise MEMS sensor and therefore the offset can slightly change after mounting the
sensor onto a printed circuit board or exposing it to extensive mechanical stress. Offset
changes little over temperature, see Zero-g level change vs. temperature . The Zero-g level
of an individual sensor is stable over lifetime. The Zero-g level tolerance describes the range
of Zero-g levels of a population of sensors.
2.5.3 Self test
Self test allows to test the mechanical and electric part of the sensor, allowing the seismic
mass to be moved by means of an electrostatic test-force. The self-test function is off when
the self-test bit of CTRL_REG1 (control register 1) is programmed to 0 . When the self-test
bit of CTRL_REG1 is programmed to 1 an actuation force is applied to the sensor,
simulating a definite input acceleration. In this case the sensor outputs will exhibit a change
in their DC levels which is related to the selected full scale and depending on the Supply
Voltage through the device sensitivity. When Self Test is activated, the device output level is
given by the algebraic sum of the signals produced by the acceleration acting on the sensor
and by the electrostatic test-force. If the output signals change within the amplitude
specified inside Table 3 or 4 then the sensor is working properly and the parameters of the
interface chip are within the defined specification.
15/49
Functionality AIS326DQ
3 Functionality
The AIS326DQ is a high performance, low-power, digital output 3-axes linear accelerometer
packaged in a QFN package. The complete device includes a sensing element and an IC
interface able to take the information from the sensing element and to provide a signal to the
external world through an SPI serial interface.
3.1 Sensing element
A proprietary process is used to create a surface micro-machined accelerometer. The
technology allows to carry out suspended silicon structures which are attached to the
substrate in a few points called anchors and are free to move in the direction of the sensed
acceleration. To be compatible with the traditional packaging techniques a cap is placed on
top of the sensing element to avoid blocking the moving parts during the moulding phase of
the plastic encapsulation.
When an acceleration is applied to the sensor the proof mass displaces from its nominal
position, causing an imbalance in the capacitive half-bridge. This imbalance is measured
using charge integration in response to a voltage pulse applied to the sense capacitor.
At steady state the nominal value of the capacitors are few pF and when an acceleration is
applied the maximum variation of the capacitive load is up to 100 pF.
3.2 IC interface
The complete measurement chain is composed by a low-noise capacitive amplifier which
converts into an analog voltage the capacitive unbalancing of the MEMS sensor and by
three Ł" analog-to-digital converters, one for each axis, that translate the produced signal
into a digital bitstream.
The Ł" converters are coupled with dedicated reconstruction filters which remove the high
frequency components of the quantization noise and provide low rate and high resolution
digital words.
The charge amplifier and the Ł" converters are operated respectively at 61.5 kHz and 20.5
kHz.
The data rate at the output of the reconstruction depends on the user selected decimation
factor (DF) and spans from 40 Hz to 2560 Hz.
The acceleration data may be accessed through an SPI interface thus making the device
particularly suitable for direct interfacing with a microcontroller.
The AIS326DQ features a data-ready signal (RDY) which indicates when a new set of
measured acceleration data is available thus simplifying data synchronization in digital
system employing the device itself.
The AIS326DQ may also be configured to generate an inertial wake-up, direction detection
and free-fall interrupt signal accordingly to a programmed acceleration event along the
enabled axes.
16/49
AIS326DQ Functionality
3.3 Factory calibration
The IC interface is factory calibrated for sensitivity (So) and Zero-g level (Off).
The trimming values are stored inside the device by a non volatile structure. Any time the
device is turned on, the trimming parameters are downloaded into the registers to be
employed during the normal operation. This allows the user to employ the device without
further calibration.
17/49
Application hints AIS326DQ
4 Application hints
Figure 4. AIS326DQ electrical connection
1
Z
28 22
Y
1 21
AIS326DQ X
10uF
(TOP VIEW)
7 15
DIRECTIONS OF THE
100nF
814
DETECTABLE
ACCELERATIONS
Vdd_IO
Vdd
GND
Digital signal from/to signal controller. Signal s levels are defined by proper selection of Vdd_IO
The device core is supplied through Vdd line while the I/O pads are supplied through
Vdd_IO line. Power supply decoupling capacitors (100 nF ceramic, 10 F Al) should be
placed as near as possible to the pin 3 of the device (common design practice).
All the voltage and ground supplies must be present at the same time to have proper
behavior of the IC (refer to Figure 4). It is possible to remove Vdd maintaining Vdd_IO
without blocking the communication busses. In this condition the measurement chain is
powered off.
The functionality of the device and the measured acceleration data is selectable and
accessible through the SPI interface.
The functions, the thresholds and the timing of the interrupt pin (INT) can be completely
programmed by the user through the SPI interface.
18/49
CS
SPC
SDO
SDI/SDO
RDY/INT
AIS326DQ Digital interface
5 Digital interface
The registers embedded inside the AIS326DQ may be accessed through SPI serial
interface. The latter may be SW configured to operate either in 3-wire or 4-wire interface
mode.
Table 7. Serial interface pin description
Pin name Pin description
CS Chip select (logic 0: SPI enabled, logic 1: SPI disabled)
SPC SPI serial port clock
SPI serial data input (SDI)
SDI/SDO
3-wire interface serial data output (SDO)
SDO SPI serial data output (SDO)
The embedded registers may be accessed also through an I2C interface. For I2C operation
refer to LIS3LV02DQ datasheet.
5.1 SPI bus interface
The AIS326DQ SPI is a bus slave. The SPI allows to write and read the registers of the
device.
The serial interface interacts with the outside world with 4 wires: CS, SPC, SDI and SDO.
Figure 5. Read and write protocol
CS
SPC
SDI
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
RW
MS AD5 AD4 AD3 AD2 AD1 AD0
SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
CS is the serial port enable and it is controlled by the SPI master. It goes low at the start of
the transmission and goes back high at the end.
SPC is the Serial Port Clock and it is controlled by the SPI master. It is stopped high when
CS is high (no transmission).
SDI and SDO are respectively the serial port data input and output. Those lines are driven
at the falling edge of SPC and should be captured at the rising edge of SPC.
Both the read register and write register commands are completed in 16 clock pulses or in
multiple of 8 in case of multiple byte read/write. Bit duration is the time between two falling
edges of SPC. The first bit (bit 0) starts at the first falling edge of SPC after the falling edge
19/49
Digital interface AIS326DQ
of CS while the last bit (bit 15, bit 23, ...) starts at the last falling edge of SPC just before the
rising edge of CS.
bit 0: RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0)
from the device is read. In latter case, the chip will drive SDO at the start of bit 8.
bit 1: MS bit. When 0, the address will remain unchanged in multiple read/write commands.
When 1, the address will be auto increased in multiple read/write commands.
bit 2-7: address AD(5:0). This is the address field of the indexed register.
bit 8-15: data DI(7:0) (write mode). This is the data that will be written into the device (MSb
first).
bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb
first).
In multiple read/write commands further blocks of 8 clock periods will be added. When MS
bit is 0 the address used to read/write data remains the same for every block. When MS bit
is 1 the address used to read/write data is increased at every block.
The function and the behavior of SDI and SDO remain unchanged.
5.1.1 SPI Read
Figure 6. SPI read protocol
CS
SPC
SDI
RW
MS AD5 AD4 AD3 AD2 AD1 AD0
SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
The SPI Read command is performed with 16 clock pulses. Multiple byte read command is
performed adding blocks of 8 clock pulses at the previous one.
bit 0: READ bit. The value is 1.
bit 1: MS bit. When 0 do not increment address, when 1 increment address in multiple
reading.
bit 2-7: address AD(5:0). This is the address field of the indexed register.
bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb
first).
bit 16-... : data DO(...-8). Further data in multiple byte reading.
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AIS326DQ Digital interface
Figure 7. Multiple bytes SPI read protocol (2 bytes example)
CS
SPC
SDI
RW
MS AD5 AD4 AD3 AD2 AD1 AD0
SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DO15 DO13 DO11 DO9 DO8
DO14 DO12 DO10
5.1.2 SPI Write
Figure 8. SPI Write protocol
CS
SPC
SDI
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
RW
MS AD5 AD4 AD3 AD2 AD1 AD0
The SPI Write command is performed with 16 clock pulses. Multiple byte write command is
performed adding blocks of 8 clock pulses at the previous one.
bit 0: WRITE bit. The value is 0.
bit 1: MS bit. When 0 do not increment address, when 1 increment address in multiple
writing.
bit 2 -7: address AD(5:0). This is the address field of the indexed register.
bit 8-15: data DI(7:0) (write mode). This is the data that will be written inside the device
(MSb first).
bit 16-... : data DI(...-8). Further data in multiple byte writing.
Figure 9. Multiple bytes SPI write protocol (2 bytes example)
CS
SPC
SDI
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8
RW
MS
AD5 AD4 AD3 AD2 AD1 AD0
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Digital interface AIS326DQ
5.1.3 SPI Read in 3-wires mode
3-wires mode is entered by setting to 1 bit SIM (SPI serial interface mode selection) in
CTRL_REG2.
Figure 10. SPI read protocol in 3-wires mode
CS
SPC
SDI/O
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
RW
MS AD5 AD4 AD3 AD2 AD1 AD0
The SPI read command is performed with 16 clock pulses:
bit 0: READ bit. The value is 1.
bit 1: MS bit. When 0 do not increment address, when 1 increment address in multiple
reading.
bit 2-7: address AD(5:0). This is the address field of the indexed register.
bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb
first).
Multiple read command is also available in 3-wires mode.
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AIS326DQ Register mapping
6 Register mapping
The table given below provides a listing of the 8 bit registers embedded in the device and
the related address.
Table 8. Registers address map
Register address
Register name Type Default Comment
Binary Hex
rw 0000000 - 0001110 00 - 0E Reserved
WHO_AM_I r 0001111 0F 00111010 Dummy register
rw 0010000 - 0010101 10 - 15 Reserved
OFFSET_X rw 0010110 16 Calibration Loaded at boot
OFFSET_Y rw 0010111 17 Calibration Loaded at boot
OFFSET_Z rw 0011000 18 Calibration Loaded at boot
GAIN_X rw 0011001 19 Calibration Loaded at boot
GAIN_Y rw 0011010 1A Calibration Loaded at boot
GAIN_Z rw 0011011 1B Calibration Loaded at boot
0011100 -0011111 1C-1F Reserved
CTRL_REG1 rw 0100000 20 00000111
CTRL_REG2 rw 0100001 21 00000000
CTRL_REG3 rw 0100010 22 00001000
HP_FILTER RESET r 0100011 23 dummy Dummy register
0100100-0100110 24-26 Not used
STATUS_REG rw 0100111 27 00000000
OUTX_L r 0101000 28 output
OUTX_H r 0101001 29 output
OUTY_L r 0101010 2A output
OUTY_H r 0101011 2B output
OUTZ_L r 0101100 2C output
OUTZ_H r 0101101 2D output
r 0101110 2E Reserved
0101111 2F Not used
FF_WU_CFG rw 0110000 30 00000000
FF_WU_SRC rw 0110001 31 00000000
FF_WU_ACK r 0110010 32 dummy Dummy register
0110011 33 Not used
FF_WU_THS_L rw 0110100 34 00000000
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Register mapping AIS326DQ
Table 8. Registers address map (continued)
Register address
Register name Type Default Comment
Binary Hex
FF_WU_THS_H rw 0110101 35 00000000
FF_WU_DURATION rw 0110110 36 00000000
0110111 37 Not used
DD_CFG rw 0111000 38 00000000
DD_SRC rw 0111001 39 00000000
DD_ACK r 0111010 3A dummy Dummy register
0111011 3B Not used
DD_THSI_L rw 0111100 3C 00000000
DD_THSI_H rw 0111101 3D 00000000
DD_THSE_L rw 0111110 3E 00000000
DD_THSE_H rw 0111111 3F 00000000
1000000-1111111 40-7F Reserved
Registers marked as Reserved must not be changed. The writing to those registers may
cause permanent damages to the device.
The content of the registers that are loaded at boot should not be changed. They contain the
factory calibration values. Their content is automatically restored when the device is
powered up.
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AIS326DQ Register description
7 Register description
The device contains a set of registers which are used to control its behavior and to retrieve
acceleration data. The registers 7.2 to 7.7 contain the factory calibration values, it is not
necessary to change their value for normal device operation.
7.1 WHO_AM_I (0Fh)
Table 9. Register
W7 W6 W5 W4 W3 W2 W1 W0
Table 10. Register description
W7, W0 AIS326DQ physical address equal to 3Ah
Addressing this register the physical address of the device is returned. For AIS326DQ the
physical address assigned in factory is 3Ah.
7.2 OFFSET_X (16h)
Table 11. OFFSET_X register
OX7 OX6 OX5 OX4 OX3 OX2 OX1 OX0
Table 12. OFFSET_X register description
OX7, OX0 Digital offset trimming for X-Axis
7.3 OFFSET_Y (17h)
Table 13. OFFSET_Y register
OY7 OY6 OY5 OY4 OY3 OY2 OY1 OY0
Table 14. OFFSET_Y register description
OY7, OY0 Digital offset trimming for Y-Axis
7.4 OFFSET_Z (18h)
Table 15. OFFSET_Z register
OZ7 OZ6 OZ5 OZ4 OZ3 OZ2 OZ1 OZ0
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Register description AIS326DQ
Table 16. OFFSET_Z register description
OZ7, OZ0 Digital offset trimming for Z-Axis
7.5 GAIN_X (19h)
Table 17. GAIN_X register
GX7 GX6 GX5 GX4 GX3 GX2 GX1 GX0
Table 18. GAIN_X register description
GX7, GX0 Digital gain trimming for X-Axis
7.6 GAIN_Y (1Ah)
Table 19. GAIN_Y register
GY7 GY6 GY5 GY4 GY3 GY2 GY1 GY0
Table 20. GAIN_Y register description
GY7, GY0 Digital gain trimming for Y-Axis
7.7 GAIN_Z (1Bh)
Table 21. GAIN_Z register
GZ7 GZ6 GZ5 GZ4 GZ3 GZ2 GZ1 GZ0
Table 22. GAIN_Z register description
GZ7, GZ0 Digital gain trimming for Z-Axis
7.8 CTRL_REG1 (20h)
Table 23. CTRL_REG1 register
PD1 PD0 DF1 DF0 ST Zen Yen Xen
Table 24. CTRL_REG1 register description
Power down control
PD1, PD0
(00: power-down mode; 01, 10, 11: device on)
Decimation factor control
DF1, DF0
(00: decimate by 512; 01: decimate by 128; 10: decimate by 32; 11: decimate by 8)
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AIS326DQ Register description
Table 24. CTRL_REG1 register description (continued)
Self test enable
ST
(0: normal mode; 1: self-test active)
Z-axis enable
Zen
(0: axis off; 1: axis on)
Y-axis enable
Yen
(0: axis off; 1: axis on)
X-axis enable
Xen
(0: axis off; 1: axis on)
PD1, PD0 bit allows to turn the device out of power-down mode. The device is in power-
down mode when PD1, PD0= 00 (default value after boot). The device is in normal mode
when either PD1 or PD0 is set to 1.
DF1, DF0 bit allows to select the data rate at which acceleration samples are produced. The
default value is 00 which corresponds to a data-rate of 40 Hz. By changing the content of
DF1, DF0 to 01 , 10 and 11 the selected data-rate will be set respectively equal to
160 Hz, 640 Hz and to 2560 Hz.
ST bit is used to activate the self test function. When the bit is set to one, an output change
will occur to the device outputs (refer to table 2 and 3 for specification) thus allowing to
check the functionality of the whole measurement chain.
Zen bit enables the Z-axis measurement channel when set to 1. The default value is 1.
Yen bit enables the Y-axis measurement channel when set to 1. The default value is 1.
Xen bit enables the X-axis measurement channel when set to 1. The default value is 1.
7.9 CTRL_REG2 (21h)
Table 25. CTRL_REG2 register
FS BDU BLE BOOT IEN DRDY SIM DAS
Table 26. CTRL_REG2 register description
Full scale selection
FS
(0: ą2 g; 1: ą6 g)
Block data update
BDU
(0: continuous update; 1: output registers not updated between MSB and LSB
reading)
Big/little endian selection
BLE
(0: little endian; 1: big endian)
BOOT Reboot memory content
Interrupt ENable
IEN
(0: data ready on RDY pad; 1: interrupt events on RDY pad)
DRDY Enable data-ready generation
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Register description AIS326DQ
Table 26. CTRL_REG2 register description (continued)
SPI serial interface mode selection
SIM
(0: 4-wire interface; 1: 3-wire interface)
Data alignment selection
DAS
(0: 12 bit right justified; 1: 16 bit left justified)
FS bit is used to select full scale value. After the device power-up the default full scale value
is +/-2 g. In order to obtain a +/-6 g full scale it is necessary to set FS bit to 1 .
BDU bit is used to inhibit output registers update between the reading of upper and lower
register parts. In default mode (BDU = 0 ) the lower and upper register parts are updated
continuously. If it is not sure to read faster than output data rate, it is recommended to set
BDU bit to 1 . In this way, after the reading of the lower (upper) register part, the content of
that output registers is not updated until the upper (lower) part is read too.
This feature avoids reading LSB and MSB related to different samples.
BLE bit is used to select Big Endian or Little Endian representation for output registers. In
Big Endian s one MSB acceleration value is located at addresses 28h (X-axis), 2Ah (Y-axis)
and 2Ch (Z-axis) while LSB acceleration value is located at addresses 29h (X-axis), 2Bh (Y-
axis) and 2Dh (Z-axis). In Little Endian representation (Default, BLE= 0 ) the order is
inverted (refer to data register description for more details).
BOOT bit is used to refresh the content of internal registers stored in the flash memory
block. At the device power up the content of the flash memory block is transferred to the
internal registers related to trimming functions to permit a good behavior of the device itself.
If for any reason the content of trimming registers was changed it is sufficient to use this bit
to restore correct values. When BOOT bit is set to 1 the content of internal flash is copied
inside corresponding internal registers and it is used to calibrate the device. These values
are factory trimmed and they are different for every accelerometer. They permit a good
behavior of the device and normally they have not to be changed. At the end of the boot
process the BOOT bit is set again to 0 .
IEN bit is used to switch the value present on data-ready pad between Data-Ready signal
and Interrupt signal. At power up the Data-ready signal is chosen. It is however necessary to
modify DRDY bit to enable Data-Ready signal generation.
DRDY bit is used to enable Data-Ready (RDY/INT) pin activation. If DRDY bit is 0 (default
value) on Data-Ready pad a 0 value is present. If a Data-Ready signal is desired it is
necessary to set to 1 DRDY bit. Data-Ready signal goes to 1 whenever a new data is
available for all the enabled axis. For example if Z-axis is disabled, Data-Ready signal goes
to 1 when new values are available for both X and Y axis. Data-Ready signal comes back
to 0 when all the registers containing values of the enabled axis are read. To be sure not to
loose any data coming from the accelerometer data registers must be read before a new
Data-Ready rising edge is generated. In this case Data-ready signal will have the same
frequency of the data rate chosen.
SIM bit selects the SPI Serial Interface Mode. When SIM is 0 (default value) the 4-wire
interface mode is selected. The data coming from the device are sent to SDO pad. In 3-wire
interface mode output data are sent to SDA/SDI pad.
DAS bit permits to decide between 12 bit right justified and 16 bit left justified representation
of data coming from the device. The first case is the default case and the most significant
bits are replaced by the bit representing the sign.
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AIS326DQ Register description
7.10 CTRL_REG3 (22h)
Table 27. CTRL_REG3 register
ECK HPDD HPFF FDS res res CFS1 CFS0
Table 28. CTRL_REG3 register description
External Clock. Default value: 0
ECK
(0: clock from internal oscillator; 1: clock from external pad)
High Pass filter enabled for Direction Detection. Default value: 0
HPDD
(0: filter bypassed; 1: filter enabled)
High Pass filter enabled for Free-Fall and Wake-Up. Default value: 0
HPFF
(0: filter bypassed; 1: filter enabled)
Filtered Data Selection. Default value: 0
FDS
(0: internal filter bypassed; 1: data from internal filter)
High-pass filter Cut-off Frequency Selection. Default value: 00
(00: Hpc=512
CFS1, CFS0 01: Hpc=1024
10: Hpc=2048
11: Hpc=4096)
FDS bit enables (FDS=1) or bypass (FDS=0) the high pass filter in the signal chain of the
sensor.
CFS1, CFS0 bits defines the coefficient Hpc to be used to calculate the -3dB cut-off
frequency of the high pass filter:
0.318 ODRx
- -
fcutoff = -------------- " ----------------
Hpc 2
7.11 HP_FILTER_RESET (23h)
Dummy register. Reading at this address zeroes instantaneously the content of the internal
high pass-filter. Read data is not significant.
7.12 STATUS_REG (27h)
Table 29. STATUS_REG register
ZYXOR ZOR YOR XOR ZYXDA ZDA YDA XDA
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Register description AIS326DQ
Table 30. STATUS_REG register description
ZYXOR X, Y and Z axis data overrun
ZOR Z axis data overrun
YOR Y axis data overrun
XOR X axis data overrun
ZYXDA X, Y and Z axis new data available
ZDA Z axis new data available
YDA Y axis new data available
XDA X axis new data available
The content of this register is updated every ODR cycle, regardless of BDU bit value in
CTRL_REG2.
7.13 OUTX_L (28h)
Table 31. OUTX_L register
XD7 XD6 XD5 XD4 XD3 XD2 XD1 XD0
Table 32. OUTX_L register description
XD7, XD0 X axis acceleration data LSB
In big endian mode (bit BLE in CTRL_REG2 set to 1 ) the content of this register is the MSB
acceleration data and depends on bit DAS in CTRL_REG2 register as described in the
following section.
7.14 OUTX_H (29h)
Table 33. OUTX_H register
XD15 XD14 XD13 XD12 XD11 XD10 XD9 XD8
Table 34. OUTX_H register description
XD15, XD8 X axis acceleration data MSB
When reading the register in 12 bit right justified mode the most significant bits (15:12) are
replaced with bit 11 (i.e. XD15-XD12=XD11, XD11, XD11, XD11).
In big endian mode (bit BLE in CTRL_REG2 set to 1 ) the content of this register is the LSB
acceleration data.
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AIS326DQ Register description
7.15 OUTY_L (2Ah)
Table 35. OUTY_L register
YD7 YD6 YD5 YD4 YD3 YD2 YD1 YD0
Table 36. OUTY_L register description
YD7, YD0 Y axis acceleration data LSB
In big endian mode (bit BLE in CTRL_REG2 set to 1 ) the content of this register is the MSB
acceleration data and depends on bit DAS in CTRL_REG2 register as described in the
following section.
7.16 OUTY_H (2Bh)
Table 37. OUTY_H register
YD15 YD14 YD13 YD12 YD11 YD10 YD9 YD8
Table 38. OUTY_H register description
YD15, YD8 Y axis acceleration data MSB
When reading the register in 12 bit right justified mode the most significant bits (15:12) are
replaced with bit 11 (i.e. YD15-YD12=YD11, YD11, YD11, YD11).
In big endian mode (bit BLE in CTRL_REG2 set to 1 ) the content of this register is the LSB
acceleration data.
7.17 OUTZ_L (2Ch)
Table 39. OUTZ_L register
ZD7 ZD6 ZD5 ZD4 ZD3 ZD2 ZD1 ZD0
Table 40. OUTZ_L register description
ZD7, ZD0 Z axis acceleration data LSB
In big endian mode (bit BLE in CTRL_REG2 set to 1 ) the content of this register is the MSB
acceleration data and depends on bit DAS in CTRL_REG2 register as described in the
following section.
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Register description AIS326DQ
7.18 OUTZ_H (2Dh)
Table 41. OUTZ_H register
ZD15 ZD14 ZD13 ZD12 ZD11 ZD10 ZD9 ZD8
Table 42. OUTZ_H register description
ZD15, ZD8 Z axis acceleration data MSB
When reading the register in 12 bit right justified mode the most significant bits (15:12) are
replaced with bit 11 (i.e. ZD15-ZD12=ZD11, ZD11, ZD11, ZD11).
In big endian mode (bit BLE in CTRL_REG2 set to 1 ) the content of this register is the LSB
acceleration data.
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AIS326DQ Register description
7.19 FF_WU_CFG (30h)
Table 43. FF_WU_CFG register
AOI LIR ZHIE ZLIE YHIE YLIE XHIE XLIE
Table 44. FF_WU_CFG register description
And/Or combination of Interrupt events. Default value: 0.
AOI (0: OR combination of interrupt events;
1: AND combination of interrupt events)
Latch interrupt request. Default value: 0.
LIR (0: interrupt request not latched;
1: interrupt request latched)
Enable Interrupt request on Z High event. Default value: 0.
ZHIE (0: disable interrupt request;
1: enable interrupt request on measured accel. value higher than preset threshold)
Enable Interrupt request on Z Low event. Default value: 0.
ZLIE (0: disable interrupt request;
1: enable interrupt request on measured accel. value lower than preset threshold)
Enable Interrupt request on Y High event. Default value: 0.
YHIE (0: disable interrupt request;
1: enable interrupt request on measured accel. value higher than preset threshold)
Enable Interrupt request on Y Low event. Default value: 0.
YLIE (0: disable interrupt request;
1: enable interrupt request on measured accel. value lower than preset threshold)
Enable Interrupt request on X High event. Default value: 0.
XHIE (0: disable interrupt request;
1: enable interrupt request on measured accel. value higher than preset threshold)
Enable Interrupt request on X Low event. Default value: 0.
XLIE (0: disable interrupt request;
1: enable interrupt request on measured accel. value lower than preset threshold)
Free-fall and inertial wake-up configuration register.
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Register description AIS326DQ
7.20 FF_WU_SRC (31h)
Table 45. FF_WU_SRC register
X IA ZHZLYHYLXHXL
Table 46. FF_WU_SRC register description
Interrupt Active. Default value: 0
IA (0: no interrupt has been generated;
1: one or more interrupt events have been generated)
Z High. Default value: 0
ZH
(0: no interrupt; 1: Z High event has occurred)
Z Low. Default value: 0
ZL
(0: no interrupt; 1: Z Low event has occurred)
Y High. Default value: 0
YH
(0: no interrupt; 1: Y High event has occurred)
Y Low. Default value: 0
YL
(0: no interrupt; 1: Y Low event has occurred)
X High. Default value: 0
XH
(0: no interrupt; 1: X High event has occurred)
X Low. Default value: 0
XL
(0: no interrupt; 1: X Low event has occurred)
7.21 FF_WU_ACK (32h)
Dummy register. If LIR bit in FF_WU_CFG register is set to 1 , a reading at this address
refreshes the FF_WU_SRC register. Read data is not significant.
7.22 FF_WU_THS_L (34h)
Table 47. FF_WU_THS_L register
THS7 THS6 THS5 THS4 THS3 THS2 THS1 THS0
Table 48. FF_WU_THS_L register description
THS7, THS0 Free-fall / inertial wake up acceleration threshold LSB
7.23 FF_WU_THS_H (35h)
Table 49. FF_WU_THS_H register
THS15 THS14 THS13 THS12 THS11 THS10 THS9 THS8
Table 50. FF_WU_THS_H register description
THS15, THS8 Free-fall / inertial wake up acceleration threshold MSB
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AIS326DQ Register description
7.24 FF_WU_DURATION (36h)
Table 51. FF_WU_DURATION register
FWD7 FWD6 FWD5 FWD4 FWD3 FWD2 FWD1 FWD0
Table 52. FF_WU_DURATION register description
FWD7, FWD0 Minimum duration of the Free-fall/Wake-up event
This register sets the minimum duration of the free-fall/wake-up event to be recognized.
FF_WU_DURATION (Dec)
Duration(s) = ------------------------------------------------------------------------
ODR
7.25 DD_CFG (38h)
Table 53. DD_CFG register
IEND LIR ZHIE ZLIE YHIE YLIE XHIE XLIE
Table 54. DD_CFG register description
Interrupt enable on direction change. Default value: 0
IEND (0: disabled;
1: interrupt signal enabled)
Latch Interrupt request into DD_SRC reg with the DD_SRC reg cleared by reading
DD_ACK reg. Default value: 0.
LIR
(0: interrupt request not latched;
1: interrupt request latched)
Enable interrupt generation on Z high event. Default value: 0
ZHIE (0: disable interrupt request;
1: enable interrupt request on measured accel. value higher than preset threshold)
Enable interrupt generation on Z low event. Default value: 0
ZLIE (0: disable interrupt request;
1: enable interrupt request on measured accel. value lower than preset threshold)
Enable interrupt generation on Y high event. Default value: 0
YHIE (0: disable interrupt request;
1: enable interrupt request on measured accel. value higher than preset threshold)
Enable interrupt generation on Y low event. Default value: 0
YLIE (0: disable interrupt request;
1: enable interrupt request on measured accel. value lower than preset threshold)
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Register description AIS326DQ
Table 54. DD_CFG register description (continued)
Enable interrupt generation on X high event. Default value: 0
XHIE (0: disable interrupt request;
1: enable interrupt request on measured accel. value higher than preset threshold)
Enable interrupt generation on X low event. Default value: 0
XLIE (0: disable interrupt request;
1: enable interrupt request on measured accel. value lower than preset threshold)
Direction-detector configuration register.
7.26 DD_SRC (39h)
Table 55. DD_SRC register
X IA ZHZLYHYLXHXL
Table 56. DD_SRC register description
Interrupt event from direction change.
IA (0: no direction changes detected;
1: direction has changed from previous measurement)
Z High. Default value: 0
ZH (0: Z below THSI threshold;
1: Z accel. exceeding THSE threshold along positive direction of acceleration axis)
Z Low. Default value: 0
ZL (0: Z below THSI threshold;
1: Z accel. exceeding THSE threshold along negative direction of acceleration axis)
Y High. Default value: 0
YH (0: Y below THSI threshold;
1: Y accel. exceeding THSE threshold along positive direction of acceleration axis)
Y Low. Default value: 0
YL (0: Y below THSI threshold;
1: Y accel. exceeding THSE threshold along negative direction of acceleration axis)
X High. Default value: 0
XH (0: X below THSI threshold;
1: X accel. exceeding THSE threshold along positive direction of acceleration axis)
X Low. Default value: 0
XL (0: X below THSI threshold;
1: X accel. exceeding THSE threshold along negative direction of acceleration axis)
Direction detector source register.
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AIS326DQ Register description
7.27 DD_ACK (3Ah)
Dummy register. If LIR bit in DD_CFG register is set to 1 , a reading at this address
refreshes the DD_SRC register. Read data is not significant.
7.28 DD_THSI_L (3Ch)
Table 57. DD_THSI_L register
THSI7 THSI6 THSI5 THSI4 THSI3 THSI2 THSI1 THSI0
Table 58. DD_THSI_L register description
THSI7, THSI0 Direction detection internal threshold LSB
7.29 DD_THSI_H (3Dh)
Table 59. DD_THSI_H register
THSI15 THSI14 THSI13 THSI12 THSI11 THSI10 THSI9 THSI8
Table 60. DD_THSI_H register description
THSI15, THSI8 Direction detection internal threshold MSB
7.30 DD_THSE_L (3Eh)
Table 61. DD_THSE_L register
THSE7 THSE6 THSE5 THSE4 THSE3 THSE2 THSE1 THSE0
Table 62. DD_THSE_L register description
THSE7, THSE0 Direction detection external threshold LSB
7.31 DD_THSE_H (3Fh)
Table 63. DD_THSE_H register
THSE15 THSE14 THSE13 THSE12 THSE11 THSE10 THSE9 THSE8
Table 64. DD_THSE_H register description
THSE15, THSE8 Direction detection external threshold MSB
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Typical performance characteristics AIS326DQ
8 Typical performance characteristics
8.1 Mechanical characteristics at 25 C
Figure 11. X-axis zero-g level at 3.3 V Figure 12. X-axis sensitivity at 3.3 V
45 30
40
25
35
30 20
25
15
20
15 10
10
5
5
0 0
-80 -60 -40 -20 0 20 40 60 80 940 960 980 1000 1020 1040 1060 1080 1100 1120
Zero-g Level Offset [mg] Sensitivity [LSB/g]
Figure 13. Y-axis zero-g level at 3.3 V Figure 14. Y-axis sensitivity at 3.3 V
40 30
35
25
30
20
25
20 15
15
10
10
5
5
0 0
-80 -60 -40 -20 0 20 40 60 80 940 960 980 1000 1020 1040 1060 1080 1100 1120
Zero-g Level Offset [mg] Sensitivity [LSB/g]
Figure 15. Z-axis zero-g level at 3.3 V Figure 16. Z-axis sensitivity at 3.3 V
30 35
30
25
25
20
20
15
15
10
10
5
5
0 0
-80 -60 -40 -20 0 20 40 60 80 940 960 980 1000 1020 1040 1060 1080 1100 1120
Zero-g Level Offset [mg] Sensitivity [LSB/g]
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Percent of parts [%]
Percent of parts [%]
Percent of parts [%]
Percent of parts [%]
Percent of parts [%]
Percent of parts [%]
AIS326DQ Typical performance characteristics
8.2 Mechanical characteristics at -40 C
Figure 17. X-axis zero-g level at 3.3 V Figure 18. X-axis sensitivity at 3.3 V
40 30
35
25
30
20
25
20 15
15
10
10
5
5
0 0
-80 -60 -40 -20 0 20 40 60 80 940 960 980 1000 1020 1040 1060 1080 1100 1120
Zero-g Level Offset [mg] Sensitivity [LSB/g]
Figure 19. Y-axis zero-g level at 3.3 V Figure 20. Y-axis sensitivity at 3.3 V
45 30
40
25
35
30 20
25
15
20
15 10
10
5
5
0 0
-80 -60 -40 -20 0 20 40 60 80 940 960 980 1000 1020 1040 1060 1080 1100 1120
Zero-g Level Offset [mg] Sensitivity [LSB/g]
Figure 21. Z-axis zero-g level at 3.3 V Figure 22. Z-axis sensitivity at 3.3 V
25 30
25
20
20
15
15
10
10
5
5
0 0
-80 -60 -40 -20 0 20 40 60 80 940 960 980 1000 1020 1040 1060 1080 1100 1120
Zero-g Level Offset [mg] Sensitivity [LSB/g]
39/49
Percent of parts [%]
Percent of parts [%]
Percent of parts [%]
Percent of parts [%]
Percent of parts [%]
Percent of parts [%]
Typical performance characteristics AIS326DQ
8.3 Mechanical characteristics at 105 C
Figure 23. X-axis zero-g level at 3.3 V Figure 24. X-axis sensitivity at 3.3 V
25 30
25
20
20
15
15
10
10
5
5
0 0
-100 -80 -60 -40 -20 0 20 40 60 80 100 920 940 960 980 1000 1020 1040 1060 1080 1100
Zero-g Level Offset [mg] Sensitivity [LSB/g]
Figure 25. Y-axis zero-g level at 3.3 V Figure 26. Y-axis sensitivity at 3.3 V
35 30
30
25
25
20
20
15
15
10
10
5
5
0 0
-100 -80 -60 -40 -20 0 20 40 60 80 100 940 960 980 1000 1020 1040 1060 1080 1100 1120
Zero-g Level Offset [mg] Sensitivity [LSB/g]
Figure 27. Z-axis zero-g level at 3.3 V Figure 28. Z-axis sensitivity at 3.3 V
25 30
25
20
20
15
15
10
10
5
5
0 0
-150 -100 -50 0 50 100 150 920 940 960 980 1000 1020 1040 1060 1080 1100
Zero-g Level Offset [mg] Sensitivity [LSB/g]
40/49
Percent of parts [%]
Percent of parts [%]
Percent of parts [%]
Percent of parts [%]
Percent of parts [%]
Percent of parts [%]
AIS326DQ Typical performance characteristics
8.4 Mechanical characteristics derived from measurement in the
-40 C to +105 C temperature range
Figure 29. X-axis zero-g level change vs. Figure 30. X-axis sensitivity change vs.
temperature at 3.3 V temperature at 3.3 V
100 5
80 4
60 3
40 2
20 1
0 0
-20 -1
-40 -2
-60 -3
-80 -4
-100 -5
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
Temp [oC] Temp [oC]
Figure 31. Y-axis zero-g level change vs. Figure 32. Y-axis sensitivity change vs.
temperature at 3.3 V temperature at 3.3 V
100 5
80 4
60 3
40 2
20 1
0 0
-20 -1
-40 -2
-60 -3
-80 -4
-100 -5
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
Temp [oC] Temp [oC]
Figure 33. Z-axis zero-g level change vs. Figure 34. Z-axis sensitivity change vs.
temperature at 3.3 V temperature at 3.3 V
100 5
80 4
60 3
40 2
20 1
0 0
-20 -1
-40 -2
-60 -3
-80 -4
-100 -5
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
Temp [oC] Temp [oC]
41/49
Sensitivity [%]
Zero-g Level [mg]
Sensitivity [%]
Zero-g Level [mg]
Sensitivity [%]
Zero-g Level [mg]
Typical performance characteristics AIS326DQ
8.5 Electro-mechanical characteristics at 25 C
Figure 35. X and Y axes zero-g level as Figure 36. X and Y axes sensitivity as function
function of supply voltage of supply voltage
80 5
4
60
3
40
2
20
1
0 0
-1
-20
-2
-40
-3
-60
-4
-80 -5
3 3.1 3.2 3.3 3.4 3.5 3.6 3 3.1 3.2 3.3 3.4 3.5 3.6
Vdd [V] Vdd [V]
Figure 37. Z axis zero-g level as function of Figure 38. Z axis sensitivity as function of
supply voltage supply voltage
80 5
4
60
3
40
2
20
1
0 0
-1
-20
-2
-40
-3
-60
-4
-80 -5
3 3.1 3.2 3.3 3.4 3.5 3.6 3 3.1 3.2 3.3 3.4 3.5 3.6
Vdd [V] Vdd [V]
42/49
Normalized Sensitivity [%]
Normalized Zero-g Level [mg]
Normalized Sensitivity [%]
Normalized Zero-g Level [mg]
AIS326DQ Typical performance characteristics
8.6 Electrical characteristics at 25 C
Figure 39. Current consumption in power- Figure 40. Current consumption in operational
down mode (Vdd=3.3 V) mode (Vdd=3.3 V)
25 25
20 20
15 15
10 10
5 5
0 0
-2 -1 0 1 2 3 4 5 6 7 500 550 600 650 700 750 800 850
Current consumption [uA] Current consumption [uA]
8.7 Electrical characteristics at -40 C
Figure 41. Current consumption in power- Figure 42. Current consumption in operational
down mode (Vdd=3.3 V) mode (Vdd=3.3 V)
30 25
25
20
20
15
15
10
10
5
5
0 0
-2 -1 0 1 2 3 4 5 6 7 500 550 600 650 700 750 800 850
Current consumption [uA] Current consumption [uA]
8.8 Electrical characteristics at 105 C
Figure 43. Current consumption in power- Figure 44. Current consumption in operational
down mode (Vdd=3.3 V) mode (Vdd=3.3 V)
30 35
30
25
25
20
20
15
15
10
10
5
5
0 0
-2 -1 0 1 2 3 4 5 6 7 500 550 600 650 700 750 800 850
Current consumption [uA] Current consumption [uA]
43/49
Percent of parts [%]
Percent of parts [%]
Percent of parts [%]
Percent of parts [%]
Percent of parts [%]
Percent of parts [%]
Soldering information AIS326DQ
9 Soldering information
The QFPN-28 package is compliant with the ECOPACK, RoHS and Green standard.
It is qualified for soldering heat resistance according to JEDEC J-STD-020C, in MSL3
condition.
Land pattern and soldering recommendations are also available at www.st.com/.
9.1 General guidelines about soldering surface mount
accelerometer
As common PCB design and industrial practice when considering accelerometer soldering,
there are always 3 elements to take into consideration:
1. PCB with its own conductive layers (i.e. copper) and other organic materials used for
board protection and dielectric isolation.
2. ACCELEROMETER to be mounted on the board. Accelerometer senses acceleration,
but it senses also the mechanical stress coming from the board. This stress is
minimized with simple PCB design rules.
3. SOLDERING PASTE like SnAgCu. This soldering paste can be dispensed on the board
with a screen printing method through a stencil. The pattern of the soldering paste on
the PCB is given by the stencil mask itself.
9.2 PCB design guidelines
PCB land and solder masking general recommendations are shown in Figure 45. Refer to
Figure 46 for specific device size, land count and pitch.
It is recommended to open solder mask external to PCB land;
It is mandatory, for correct device functionality, that some clearance is ensured to be
present between accelerometer thermal pad and PCB. In order to obtain this clearance
it is recommended to open the PCB thermal pad solder mask;
The area below the sensor (on the same side of the board) must be defined as keep-
out area. It is strongly recommended not to place any structure in top metal layer
underneath the sensor;
Traces connected to pads should be as much symmetric as possible. Symmetry and
balance for pad connection will help component self alignment and will lead to a better
control of solder paste reduction after reflow;
For better performances over temperature it is strongly recommended not to place
large insertion components like buttons or shielding boxes at distance less than 2 mm
from the sensor;
Central die pad and Pin 1 Indicator are physically connected to GND. Leave Pin 1
Indicator unconnected during soldering.
44/49
AIS326DQ Soldering information
9.2.1 PCB design rules
Figure 45. Recommended land and solder mask design for QFPN packages
PACKAGE FOOTPRINT
PCB LAND
SOLDER MASK OPENING
PCB THERMAL PAD NOT TO
BE DESIGNED ON PCB
PCB THERMAL PAD SOLDER
MASK OPENING SUGGESTED
TO INCREASE DEVICE
THERMAL PAD TO PCB
CLEARANCE
C
B
D
A
A = Clearance from PCB land edge to solder mask opening d"0.1 mm to ensure that some
solder mask remains between PCB pads
B = PCB land length = QFPN solder pad length + 0.1 mm
C = PCB land width = QFPN solder pad width + 0.1 mm
D = PCB thermal pad solder mask opening = QFPN thermal pad side + 0.2 mm
9.3 Stencil design and solder paste application
The thickness and the pattern of the soldering paste are important for the proper
accelerometer mounting process.
Stainless steel stencils are recommended for solder paste application
A stencil thickness of 125 - 150 m (5 - 6 mils) is recommended for screen printing
The final thickness of soldering paste should allow proper cleaning of flux residuals and
clearance between sensor package and PCB
Stencil aperture should have rectangular shape with dimension up to 25 m (1mil)
smaller than PCB land
The openings of the stencil for the signal pads should be between 50% and 80% of the
PCB pad area
Optionally, for better solder paste release, the aperture walls should be trapezoidal and
the corners rounded
The fine pitch of the IC leads requires accurate alignment of the stencil to the printed
circuit board. The stencil and printed circuit assembly should be aligned to within 25 m
(1 mil) prior to application of the solder paste.
45/49
Soldering information AIS326DQ
9.4 Process consideration
In case of use of no self-cleaning solder paste it is mandatory proper washing of the
board after soldering to eliminate any possible source of leakage between adjacent
pads due to flux residues
The PCB soldering profile depends on the number, size and placement of components
in the application board. It is not functional to define a specific soldering profile for the
accelerometer only. Customer should use a time and temperature reflow profile that is
derived from the PCB design and manufacturing experience.
46/49
AIS326DQ Package information
10 Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK
packages. These packages have a lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
Figure 46. QFPN-28 mechanical data and package dimensions
mm inch
OUTLINE AND
DIM.
MIN. TYP. MAX. MIN. TYP. MAX. MECHANICAL DATA
A 1.70 1.80 1.90 0.067 0.071 0.075
A1 0.05 0.002
A3 0.203 0.008
b 0.30 0.35 0.40 0.012 0.014 0.016
D 6.85 7.0 7.15 0.270 0.275 0.281
D1 4.90 5.00 5.10 0.192 0.197 0.20
E 6.85 7.0 7.15 0.270 0.275 0.281
E1 4.90 5.00 5.10 0.192 0.197 0.20
e 0.80 0.0315
L 0.45 0.55 0.65 0.018 0..022 0.025
L1 0.10 0.004
QFPN-28 (7x7x1.8mm)
Quad Flat Package No lead
ddd 0.08 0.003
7787120 C
47/49
Revision history AIS326DQ
11 Revision history
Table 65. Document revision history
Date Revision Changes
20-Aug-2008 1 Initial release.
48/49
AIS326DQ
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49/49
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