UltraCAD
Design, Inc.
DESIGN NOTE
THE EFFECTS OF VIAS ON
PCB TRACES
Background: severely distorting the characteristic
impedance of the trace.
Through the years we have worked with many
engineers who have had strong feelings about 4. A trace can move to opposite sides of an
the presence of vias on critical traces (such as individual reference plane without
fast rise time clock lines). These feelings have significant effect, but if it moves to a layer
ranged from (a) the effects of vias are so where it is referenced to a different plane
negligible that they may be used freely, to (b) then the characteristics of the trans-
their effects are so significant that vias may not mission line are severely distorted.
be used at all. Depending on your view, these
two extremes place quite different constraints 5. The effect of the first via is the greatest,
on PCB designs! but the effects of additional vias diminish
as more vias are added to the trace.
It is clear from the history of all the boards that
have ever been designed in the past that vias Unfortunately, there have been few, if any,
have little impact at lower frequencies and rise studies specifically designed to study the effects
times. It is only recently, as device rise times of vias while adequately controlling for other
and timing issues caused by faster clock variables. This is, at least in part, due to the
speeds have become critical PCB design resources required: (a) the design of a test
issues, that the concern over a via's effect on board, (b) its fabrication, and (c) the availability
PCB "transmission lines" has become a topic of of a proper suite of test equipment and the
discussion. researchers skilled in knowing how to use it.
The perceived negative effects of vias may fall Strategy:
into one of several categories:
In order to clarify some of these issues, a study
1. Vias are inherently capacitive and was designed in order to isolate and measure
change the characteristic impedance of individual effects that vias might have on traces.
the trace. A test board was designed with 9 dual stripline
traces on it, each of identical length, width, and
2. Vias cause a step-function change in thickness. There were four trace layers and
trace impedance and therefore cause three reference planes designed into the board.
reflections. Some traces had no vias on them at all --- they
were "pure" transmission lines. Others had one
3. When a trace moves from one layer to or more via "holes" along them, but the signal
another, it becomes referenced to a path did not go through the vias. Others passed
different reference plane, therefore through the via, but the signal path always
11502 NE 20th, Bellevue, WA. 98004 Phone: (206) 450-9708 FAX: (206) 450-9790
referenced the same plane. Finally, others possible to identical. Target characteristic
passed through the via in such a way that the impedance is 50&!. Layers 1, 4+5, and 8 are
stripline trace referenced a different reference
planes (4 and 5 are electrically connected as a
plane. Each trace was terminated at each end
single plane.) The three planes are isolated
with a high-performance RF 50&! connector,
from each other except for the capacitors C1
providing access for the test equipment. through C4. This configuration simulates a
normal board with separate power and ground
Each trace was evaluated with a time domain planes, capacitively filtered at some arbitrary
reflectometer, and signals were visually spot on the board. Via holes are represented
evaluated at both the input and output. by circles along the trace. They are precisely
placed along a grid that divides the trace length
This study presents a model of industry into eight equal increments. The vias them-
cooperation for the common goal of increasing selves are .028 diameter plated through holes,
understanding. The board design and project with .050 diameter pads and .075 diameter
coordination was donated by UltraCAD Design, anti-pads on the planes.
Inc. (Bellevue, WA.) Eight boards were
fabricated and donated by Dynamic Circuits, The number along each trace segment
Inc. (Milpitas, CA.) The test equipment and identifies the layer it is on. Each trace is
measurement resources were provided by terminated at each end by a 50&! RF
Professors Chi H. Chan and Yasuo Kuga at the
connector. The shell of the connector is
University of Washington's Electrical Engin-
connected to one of the three planes as
eering Department. And the Washington Tech-
indicated by the number adjacent to the
nology Center provided matching funding for
connector.
equipment and resource availability. None of
these partners had all the resources required
Each trace, in turn, was connected to an HP
to do the research on their own. Their mutual
54120B Time Domain Reflectometer (TDR) at
cooperation made this effort possible.
the left side of the board. The other end of the
trace was terminated in a 50&! load. The TDR
Procedure:
provides an output that can reflect the
impedance at any point along the trace. Two
The design of the test board is shown in
different boards were evaluated in this manner,
Figures 1 and 2. Traces on layers 2, 3, 6, and
and the results compared. In addition, a fast
7 are identical width (.008 inches), length (15
rise time pulse was applied to each trace and
inches) and thickness (one ounce copper,
the signal at the opposite end was recorded
approximately .0014 inch thick). They all are
with a high frequency storage scope.
dual stripline traces and are as close as
Figure 1
Board Schematic
Trace geometries are identical. Circles
represent vias along the traces. The
numbers on the trace segments or
connector and component pins define the
layers to which they are connected.
1 Oz Foil Layer 1
The traces reflect increasingly "worse" cases.
.0077 Pre-Preg
1 Oz Cop per Layer 2
Traces C and G (traces A and B applied to a
.008 1/1 Core
different analysis) are pure transmission lines.
1 Oz Cop per Layer 3
.0075 Pre-preg
Traces D and F have vias along them, but the
1 Oz Cop per Layer 4
.008 1/1 Core
signal does not pass through the vias. Other
1 Oz Cop per Layer 5
traces have vias through which the signal
.0075 Pre-Preg
1 Oz Cop per Layer 6
passes to various combinations of layers,
.008 1/1 Core
involving one or more reference planes.
1 Oz Cop per Layer 7
.0075 Pre-Preg
1 Oz Foil Layer 8
Results:
Finished Trace w idth 0.008
Final Thickness .067 +/- .007
Figure 3 illustrates the TDR output for Trace C,
a straight trace with no vias. It should be as
VIA Test Board
close an approximation to a "pure" transmission
Layer Stack-up
(Not to Scale)
line as can be achieved with this setup. The
"round trip" time on the output is almost exactly
Figure 2
5 nsec. Although we do not favor using "rules of
thumb", it is interesting to note that at 2 nsec per
and they should look like the trace in Figure 3.
foot, the rule of thumb for pulse propagation
In fact, while the average impedance for each
delay along a trace, this equates exactly to the
trace is about 58&! , the range of impedance is
trace length of 15 inches!
from 57 to 62&! for board 1 and from 56 to 60&!
The average measured impedance along the
for board 2.
trace is about 58&!, or about 16% over target.
These figures illustrate the practical problem of
The variation in impedance along the trace
specifying trace impedances on PCB boards.
ranges from 57.2&! to 59.5&!, or about 4%
Even under reasonably controlled conditions,
around the average.
impedance targets are hard to hit, and they
vary by several percent from board to board,
Figure 4 illustrates the TDR outputs for Trace G
from layer to layer, from trace to trace, and
for both board 1 and board 2, thus comparing
even along the same trace!
the repeatability between boards. This trace is
also a pure transmission line, but on trace layer
Figure 5 illustrates the TDR results for Trace
2. In theory, both traces should look the same
D. This trace is on layer 3 with a single via in
Figure 3
TDR output for Trace C, Layer 3
The variation in impedance along
the trace is approximately 2.3 &!
or about 4%. The "round trip"
trace length is about 5 nsec,
implying a 15" trace at a
propagation delay of 2 nsec/ft.
Figure 4
Comparative TDR outputs for
Trace G, Boards 1 and 2,
Layer 2.
Note the variation in impe-
dance not only along the trace,
but between the fabricated
boards themselves.
Figure 5
Trace D, layer 3, with a single via
in the center of the trace. The
trace does not pass through the
via.
Note that the region affected by
the via is about +/-.5 in.
Otherwise the trace closely
resembles Figure 3 (Trace C).
the middle, but the signal does not pass through
the via. Although it was not studied in this
the via to another layer. Except for the via, the
effort, the region influenced by a component
trace closely resembles Trace C (Figure 3),
pin is presumably even larger.
immediately adjacent to this trace and on the
same layer. This result is typical; trace areas
Figure 6 illustrates what happens when more
outside the influence of the vias exhibit very
vias (7 of them) are added along the trace.
similar characteristics to adjacent traces on the
Again, this trace is on layer 3 and the signal
same layer, but this similarity diminishes as the
does not pass through any via. And again,
distance to adjacent traces increases.
the area between the vias resembles Trace C
on layer 3 (with no vias) although this trace is
The impact of the via suggests that the via is
somewhat further separated from Trace C.
capacitive in nature, and the measured transient
impedance drops about 6 or 7&! (approximately The influence of the vias appears to
decrease as more vias are added. We have
12%) at the lowest point.
heard engineers describe this effect as
follows:
The influence of the via is seen over about 300
Psec of trace length around the via, or almost +/-
The first via has a significant capacitive
.5 inch, even though the maximum via geometry is
only .075 inch. This result is consistent for all vias. effect, but this effect diminishes as
This illustrates the degree that the transmission more vias are added.
line assumptions break down in the region around
Figure 6, Trace F, layer 3
with multiple vias. Traces
do not go through the vias.
Figure 7
Trace D, Layer 3
Output from Trace in response to a step-function
input. Rise time degredation is 191 Psec.
attenuation of higher order frequency
Timebase = 1.00 ns/div
harmonics from trace losses (and perhaps
Ch. 4 = 50.00 mVolts/div
connector losses) alone.
The measured rise time of Trace F (with 7
vias) was 376 Psec, suggesting the vias
"cost" another 145 Psec in rise time, or
In fact, what appears to be happening is that each
about 20 Psecs per via. Other measure-
via (and even the trace itself) causes a slight high
ments along other traces were consistent
frequency loss (to be described in more detail,
with this estimate of 20 Psec reduction in
below.) This loss in high frequency component
rise time per via.
appears to manifest itself in measurement
distortion within the TDR. Thus, the TDR appears
Interestingly enough, when the signal
to suggest decreasing effects as more vias are
passed through a via to another layer, there
added because its own measurements are being
were no additional effects that have not
distorted by the attenuation of higher frequency
already been discussed. This was true even
harmonics. This result is typical for all traces.
when the signal became referenced to a
different plane. The effect in the immediate
Another result tends to confirm this analysis.
vicinity of the via hole was the same as if the
Figure 7 illustrates the output at the end of a
signal did not pass through the via, and
typical trace as a result of a step-function input to
between the vias the traces took on the
the trace. (Figure 7 happens to illustrate Trace D.)
characteristics of layer they were on. There
The input voltage had a measured rise time of 40
was some signal degradation due to the
Psec. The output signal from Trace C had a
inherent nature of a transmission line and
measured rise time of 231 Psec, or a slowing of
because of differences in impedance along
the rise time by 191 Psec. This represents the
the trace. But using a via to transition to Other Considerations:
another layer of the same target impedance
seemed to have no additional degradation While the results of this study were consistent
than a did a via hole without a signal across traces and boards, they do raise some
transition. other questions. For example, would vias have
Conclusion: relatively more impact if traces were shorter? Or
if via geometries were larger? Or what if we
In these results, a via tended to present a targeted a different intrinsic impedance (such as
transient impedance discontinuity to a trace of 75&!)? We think not, but the question deserves
about 6&!. This would result in a negative
consideration.
reflection coefficient of about .055, or about
5%: If a via has an impact that is seen for as much as
.5 inch around the via, how do component pins
(as differentiated from the components them-
selves) impact trace impedances in dense
( R L - Z 0) 52 - 58
Á = = =.055
boards?
( R L + Z 0) 52 + 58
Although there did not seem to be any signal
Visual evaluation of various signals also
degradation when a signal passed through a via
suggested that reflections are small. (For
and became referenced to a different plane (as in
example, see Figure 7.)
the case of Trace J where the trace is alternately
referenced to the top plane -- layer 1-- and the
Vias did have a capacitive effect and tended
middle plane -- layers 4+5), it nevertheless
to attenuate the very high frequency
seems true that the signal return path must be
harmonics of the signal, as manifested in a
somewhere. And other studies have shown that
slower signal rise time. But this effect, per via,
for fast rise time pulses, the return path likes to
was about an order of magnitude less than
be "close" to the signal path. If the return paths
the losses along the trace without any vias at
are "roaming" unpredictably around the planes,
all (over the full 15 inches of trace). It would
does this have an impact for EMI radiation from
seem that for designs using components with
the board? The answer might quite likely be
rise times in the range of .5 to 1.0 nsec or
"yes."
slower (500 to 1000 Psecs), which is still
pretty fast, a 40 Psec rise time impact as a
Thus, the results disclosed by this study seem to
result of a via would appear to be relatively
be instructive, but, as always, more questions are
harmless.
raised.
Copyright 1994 by UltraCAD Design, Inc. May not be reproduced in any form without explicit and written
approval from UltraCAD.
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